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Merge branch 'master' of https://github.gatech.edu/casl/Vortex

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This commit is contained in:
Blaise Tine
2020-08-03 07:00:40 -04:00
parent 042da74778 d8bdaa2b4e
commit 72da1380ea
5 changed files with 29 additions and 24 deletions
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14
hw/opae/README
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@@ -89,8 +89,12 @@ kill -9 <pid>
lsof +D build_ase_1c lsof +D build_ase_1c
# quick off cache synthesis # quick off cache synthesis
make -C pipeline > pipeline/build.log 2>&1 & make -C pipeline clean && make -C pipeline > pipeline/build.log 2>&1 &
make -C cache > cache/build.log 2>&1 & make -C cache clean && make -C cache > cache/build.log 2>&1 &
make -C core > core/build.log 2>&1 & make -C core clean && make -C core > core/build.log 2>&1 &
make -C vortex > vortex/build.log 2>&1 & make -C vortex clean && make -C vortex > vortex/build.log 2>&1 &
make -C top > top/build.log 2>&1 & make -C top clean && make -C top > top/build.log 2>&1 &
# How to calculate the maximum operating frequency?
200 Mhz -> period = 1/200x10^6 = 5ns
if slack = +1.664 -> minimal period = 5-1.664 = 3.336 -> fmax = 1/3.336 = 300 Mhz

2
hw/rtl/VX_gpr_stage.v
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@@ -18,7 +18,7 @@ module VX_gpr_stage #(
wire [`NUM_THREADS-1:0][31:0] rs2_data; wire [`NUM_THREADS-1:0][31:0] rs2_data;
wire [`NW_BITS+`NR_BITS-1:0] raddr1; wire [`NW_BITS+`NR_BITS-1:0] raddr1;
VX_gpr_ram gpr_int_ram ( VX_gpr_ram gpr_ram (
.clk (clk), .clk (clk),
.we ({`NUM_THREADS{writeback_if.valid}} & writeback_if.thread_mask), .we ({`NUM_THREADS{writeback_if.valid}} & writeback_if.thread_mask),
.waddr ({writeback_if.warp_num, writeback_if.rd}), .waddr ({writeback_if.warp_num, writeback_if.rd}),

5
hw/rtl/fp_cores/VX_fp_fpga.v
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@@ -39,8 +39,8 @@ module VX_fp_fpga (
VX_fpnew #( VX_fpnew #(
.FMULADD (0), .FMULADD (0),
.FDIVSQRT (0), .FDIVSQRT (0),
.FNONCOMP (0), .FNONCOMP (1),
.FCONV (1) .FCONV (0)
) fp_core ( ) fp_core (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -67,6 +67,7 @@ module VX_fp_fpga (
.out_valid (fpnew_out_valid) .out_valid (fpnew_out_valid)
); );
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin for (i = 0; i < `NUM_THREADS; i++) begin
acl_fp_add fp_add ( acl_fp_add fp_add (
.clock (clk), .clock (clk),

16
hw/rtl/libs/VX_divide.v
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@@ -25,7 +25,7 @@ module VX_divide #(
wire [WIDTHN-1:0] quotient_unqual; wire [WIDTHN-1:0] quotient_unqual;
wire [WIDTHD-1:0] remainder_unqual; wire [WIDTHD-1:0] remainder_unqual;
lpm_divide quartus_div ( lpm_divide divide (
.clock (clk), .clock (clk),
.numer (numer), .numer (numer),
.denom (denom), .denom (denom),
@@ -36,13 +36,13 @@ module VX_divide #(
); );
defparam defparam
quartus_div.lpm_type = "LPM_DIVIDE", divide.lpm_type = "LPM_DIVIDE",
quartus_div.lpm_widthn = WIDTHN, divide.lpm_widthn = WIDTHN,
quartus_div.lpm_widthd = WIDTHD, divide.lpm_widthd = WIDTHD,
quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED",
quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", divide.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED",
quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", divide.lpm_hint = "MAXIMIZE_SPEED=9,LPM_REMAINDERPOSITIVE=FALSE",
quartus_div.lpm_pipeline = PIPELINE; divide.lpm_pipeline = PIPELINE;
assign quotient = quotient_unqual [WIDTHQ-1:0]; assign quotient = quotient_unqual [WIDTHQ-1:0];
assign remainder = remainder_unqual [WIDTHR-1:0]; assign remainder = remainder_unqual [WIDTHR-1:0];

16
hw/rtl/libs/VX_multiplier.v
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@@ -18,7 +18,7 @@ module VX_multiplier #(
`ifdef QUARTUS `ifdef QUARTUS
lpm_mult quartus_mult ( lpm_mult mult (
.clock (clk), .clock (clk),
.dataa (dataa), .dataa (dataa),
.datab (datab), .datab (datab),
@@ -29,13 +29,13 @@ module VX_multiplier #(
.sum (1'b0) .sum (1'b0)
); );
defparam quartus_mult.lpm_type = "LPM_MULT", defparam mult.lpm_type = "LPM_MULT",
quartus_mult.lpm_widtha = WIDTHA, mult.lpm_widtha = WIDTHA,
quartus_mult.lpm_widthb = WIDTHB, mult.lpm_widthb = WIDTHB,
quartus_mult.lpm_widthp = WIDTHP, mult.lpm_widthp = WIDTHP,
quartus_mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED", mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED",
quartus_mult.lpm_pipeline = PIPELINE, mult.lpm_pipeline = PIPELINE,
quartus_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"; mult.lpm_hint = "MAXIMIZE_SPEED=9,DEDICATED_MULTIPLIER_CIRCUITRY=YES";
`else `else
wire [WIDTHP-1:0] result_unqual; wire [WIDTHP-1:0] result_unqual;