From 28a2f77725ba274a86bc8f18d90bef7bf7493b90 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 1 Aug 2020 10:16:07 -0700 Subject: [PATCH 1/2] minor update --- hw/rtl/fp_cores/VX_fp_fpga.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/rtl/fp_cores/VX_fp_fpga.v b/hw/rtl/fp_cores/VX_fp_fpga.v index 01c65105..e120a4a0 100644 --- a/hw/rtl/fp_cores/VX_fp_fpga.v +++ b/hw/rtl/fp_cores/VX_fp_fpga.v @@ -39,8 +39,8 @@ module VX_fp_fpga ( VX_fpnew #( .FMULADD (0), .FDIVSQRT (0), - .FNONCOMP (0), - .FCONV (1) + .FNONCOMP (1), + .FCONV (0) ) fp_core ( .clk (clk), .reset (reset), @@ -67,6 +67,7 @@ module VX_fp_fpga ( .out_valid (fpnew_out_valid) ); + genvar i; for (i = 0; i < `NUM_THREADS; i++) begin acl_fp_add fp_add ( .clock (clk), From d8bdaa2b4e9c7f341de25982aa6b36019390caf2 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 1 Aug 2020 14:38:31 -0700 Subject: [PATCH 2/2] minor update --- hw/opae/README | 14 +++++++++----- hw/rtl/VX_gpr_stage.v | 2 +- hw/rtl/libs/VX_divide.v | 16 ++++++++-------- hw/rtl/libs/VX_multiplier.v | 16 ++++++++-------- 4 files changed, 26 insertions(+), 22 deletions(-) diff --git a/hw/opae/README b/hw/opae/README index f480cc92..cafa5897 100644 --- a/hw/opae/README +++ b/hw/opae/README @@ -89,8 +89,12 @@ kill -9 lsof +D build_ase_1c # quick off cache synthesis -make -C pipeline > pipeline/build.log 2>&1 & -make -C cache > cache/build.log 2>&1 & -make -C core > core/build.log 2>&1 & -make -C vortex > vortex/build.log 2>&1 & -make -C top > top/build.log 2>&1 & +make -C pipeline clean && make -C pipeline > pipeline/build.log 2>&1 & +make -C cache clean && make -C cache > cache/build.log 2>&1 & +make -C core clean && make -C core > core/build.log 2>&1 & +make -C vortex clean && make -C vortex > vortex/build.log 2>&1 & +make -C top clean && make -C top > top/build.log 2>&1 & + +# How to calculate the maximum operating frequency? +200 Mhz -> period = 1/200x10^6 = 5ns +if slack = +1.664 -> minimal period = 5-1.664 = 3.336 -> fmax = 1/3.336 = 300 Mhz \ No newline at end of file diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 0b1870b1..17992b4d 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -18,7 +18,7 @@ module VX_gpr_stage #( wire [`NUM_THREADS-1:0][31:0] rs2_data; wire [`NW_BITS+`NR_BITS-1:0] raddr1; - VX_gpr_ram gpr_int_ram ( + VX_gpr_ram gpr_ram ( .clk (clk), .we ({`NUM_THREADS{writeback_if.valid}} & writeback_if.thread_mask), .waddr ({writeback_if.warp_num, writeback_if.rd}), diff --git a/hw/rtl/libs/VX_divide.v b/hw/rtl/libs/VX_divide.v index 7a613363..3c871658 100644 --- a/hw/rtl/libs/VX_divide.v +++ b/hw/rtl/libs/VX_divide.v @@ -25,7 +25,7 @@ module VX_divide #( wire [WIDTHN-1:0] quotient_unqual; wire [WIDTHD-1:0] remainder_unqual; - lpm_divide quartus_div ( + lpm_divide divide ( .clock (clk), .numer (numer), .denom (denom), @@ -36,13 +36,13 @@ module VX_divide #( ); defparam - quartus_div.lpm_type = "LPM_DIVIDE", - quartus_div.lpm_widthn = WIDTHN, - quartus_div.lpm_widthd = WIDTHD, - quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", - quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", - quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", - quartus_div.lpm_pipeline = PIPELINE; + divide.lpm_type = "LPM_DIVIDE", + divide.lpm_widthn = WIDTHN, + divide.lpm_widthd = WIDTHD, + divide.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", + divide.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", + divide.lpm_hint = "MAXIMIZE_SPEED=9,LPM_REMAINDERPOSITIVE=FALSE", + divide.lpm_pipeline = PIPELINE; assign quotient = quotient_unqual [WIDTHQ-1:0]; assign remainder = remainder_unqual [WIDTHR-1:0]; diff --git a/hw/rtl/libs/VX_multiplier.v b/hw/rtl/libs/VX_multiplier.v index fc38e889..3322b479 100644 --- a/hw/rtl/libs/VX_multiplier.v +++ b/hw/rtl/libs/VX_multiplier.v @@ -18,7 +18,7 @@ module VX_multiplier #( `ifdef QUARTUS - lpm_mult quartus_mult ( + lpm_mult mult ( .clock (clk), .dataa (dataa), .datab (datab), @@ -29,13 +29,13 @@ module VX_multiplier #( .sum (1'b0) ); - defparam quartus_mult.lpm_type = "LPM_MULT", - quartus_mult.lpm_widtha = WIDTHA, - quartus_mult.lpm_widthb = WIDTHB, - quartus_mult.lpm_widthp = WIDTHP, - quartus_mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED", - quartus_mult.lpm_pipeline = PIPELINE, - quartus_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"; + defparam mult.lpm_type = "LPM_MULT", + mult.lpm_widtha = WIDTHA, + mult.lpm_widthb = WIDTHB, + mult.lpm_widthp = WIDTHP, + mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED", + mult.lpm_pipeline = PIPELINE, + mult.lpm_hint = "MAXIMIZE_SPEED=9,DEDICATED_MULTIPLIER_CIRCUITRY=YES"; `else wire [WIDTHP-1:0] result_unqual;