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Merge branch 'master' of https://github.gatech.edu/casl/Vortex

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This commit is contained in:
Blaise Tine
2021-09-11 18:26:08 -04:00
parent 0dfdf6cd4d 182811697e
commit 6f09fb8ba5
4 changed files with 112 additions and 43 deletions
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42
hw/rtl/Vortex_axi.v
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@@ -10,29 +10,40 @@ module Vortex_axi #(
input wire clk, input wire clk,
input wire reset, input wire reset,
// AXI write request // AXI write address channel
output wire m_axi_wvalid,
output wire m_axi_awvalid, output wire m_axi_awvalid,
output wire [AXI_TID_WIDTH-1:0] m_axi_awid, output wire [AXI_TID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen, output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize, output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst, output wire [1:0] m_axi_awburst,
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire m_axi_awlock,
output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb, output wire [3:0] m_axi_awcache,
input wire m_axi_wready, output wire [2:0] m_axi_awprot,
output wire [3:0] m_axi_awqos,
input wire m_axi_awready, input wire m_axi_awready,
// AXI read request // AXI write data channel
output wire m_axi_wvalid,
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb,
output wire m_axi_wlast,
input wire m_axi_wready,
// AXI read address channel
output wire m_axi_arvalid, output wire m_axi_arvalid,
output wire [AXI_TID_WIDTH-1:0] m_axi_arid, output wire [AXI_TID_WIDTH-1:0] m_axi_arid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen, output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize, output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst, output wire [1:0] m_axi_arburst,
output wire m_axi_arlock,
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire [3:0] m_axi_arqos,
input wire m_axi_arready, input wire m_axi_arready,
// AXI read response // AXI read data channel
input wire m_axi_rvalid, input wire m_axi_rvalid,
input wire [AXI_TID_WIDTH-1:0] m_axi_rid, input wire [AXI_TID_WIDTH-1:0] m_axi_rid,
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
@@ -62,6 +73,9 @@ module Vortex_axi #(
.AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH),
.AXI_TID_WIDTH (AXI_TID_WIDTH) .AXI_TID_WIDTH (AXI_TID_WIDTH)
) axi_adapter ( ) axi_adapter (
.clk (clk),
.reset (reset),
.mem_req_valid (mem_req_valid), .mem_req_valid (mem_req_valid),
.mem_req_rw (mem_req_rw), .mem_req_rw (mem_req_rw),
.mem_req_byteen (mem_req_byteen), .mem_req_byteen (mem_req_byteen),
@@ -75,17 +89,23 @@ module Vortex_axi #(
.mem_rsp_tag (mem_rsp_tag), .mem_rsp_tag (mem_rsp_tag),
.mem_rsp_ready (mem_rsp_ready), .mem_rsp_ready (mem_rsp_ready),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_awvalid (m_axi_awvalid), .m_axi_awvalid (m_axi_awvalid),
.m_axi_awid (m_axi_awid), .m_axi_awid (m_axi_awid),
.m_axi_awaddr (m_axi_awaddr), .m_axi_awaddr (m_axi_awaddr),
.m_axi_awlen (m_axi_awlen), .m_axi_awlen (m_axi_awlen),
.m_axi_awsize (m_axi_awsize), .m_axi_awsize (m_axi_awsize),
.m_axi_awburst (m_axi_awburst), .m_axi_awburst (m_axi_awburst),
.m_axi_awlock (m_axi_awlock),
.m_axi_awcache (m_axi_awcache),
.m_axi_awprot (m_axi_awprot),
.m_axi_awqos (m_axi_awqos),
.m_axi_awready (m_axi_awready),
.m_axi_wvalid (m_axi_wvalid),
.m_axi_wdata (m_axi_wdata), .m_axi_wdata (m_axi_wdata),
.m_axi_wstrb (m_axi_wstrb), .m_axi_wstrb (m_axi_wstrb),
.m_axi_wlast (m_axi_wlast),
.m_axi_wready (m_axi_wready), .m_axi_wready (m_axi_wready),
.m_axi_awready (m_axi_awready),
.m_axi_arvalid (m_axi_arvalid), .m_axi_arvalid (m_axi_arvalid),
.m_axi_arid (m_axi_arid), .m_axi_arid (m_axi_arid),
@@ -93,6 +113,10 @@ module Vortex_axi #(
.m_axi_arlen (m_axi_arlen), .m_axi_arlen (m_axi_arlen),
.m_axi_arsize (m_axi_arsize), .m_axi_arsize (m_axi_arsize),
.m_axi_arburst (m_axi_arburst), .m_axi_arburst (m_axi_arburst),
.m_axi_arlock (m_axi_arlock),
.m_axi_arcache (m_axi_arcache),
.m_axi_arprot (m_axi_arprot),
.m_axi_arqos (m_axi_arqos),
.m_axi_arready (m_axi_arready), .m_axi_arready (m_axi_arready),
.m_axi_rvalid (m_axi_rvalid), .m_axi_rvalid (m_axi_rvalid),

14
hw/rtl/afu/VX_avs_wrapper.v
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@@ -42,7 +42,6 @@ module VX_avs_wrapper #(
); );
localparam BANK_ADDRW = `LOG2UP(AVS_BANKS); localparam BANK_ADDRW = `LOG2UP(AVS_BANKS);
localparam OUT_REG = (AVS_BANKS > 2);
// Requests handling // Requests handling
@@ -78,9 +77,8 @@ module VX_avs_wrapper #(
`UNUSED_VAR (req_queue_size) `UNUSED_VAR (req_queue_size)
VX_fifo_queue #( VX_fifo_queue #(
.DATAW (REQ_TAG_WIDTH), .DATAW (REQ_TAG_WIDTH),
.SIZE (RD_QUEUE_SIZE), .SIZE (RD_QUEUE_SIZE)
.OUT_REG (!OUT_REG)
) rd_req_queue ( ) rd_req_queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -122,9 +120,8 @@ module VX_avs_wrapper #(
for (genvar i = 0; i < AVS_BANKS; i++) begin for (genvar i = 0; i < AVS_BANKS; i++) begin
VX_fifo_queue #( VX_fifo_queue #(
.DATAW (AVS_DATA_WIDTH), .DATAW (AVS_DATA_WIDTH),
.SIZE (RD_QUEUE_SIZE), .SIZE (RD_QUEUE_SIZE)
.OUT_REG (!OUT_REG)
) rd_rsp_queue ( ) rd_rsp_queue (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -149,8 +146,7 @@ module VX_avs_wrapper #(
VX_stream_arbiter #( VX_stream_arbiter #(
.NUM_REQS (AVS_BANKS), .NUM_REQS (AVS_BANKS),
.DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH), .DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH),
.TYPE ("R"), .TYPE ("R")
.BUFFERED (OUT_REG ? 1 : 0)
) rsp_arb ( ) rsp_arb (
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

4
hw/rtl/afu/vortex_afu.sv
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@@ -520,8 +520,8 @@ VX_mem_arb #(
.ADDR_WIDTH (LMEM_ADDR_WIDTH), .ADDR_WIDTH (LMEM_ADDR_WIDTH),
.TAG_IN_WIDTH (AVS_REQ_TAGW), .TAG_IN_WIDTH (AVS_REQ_TAGW),
.TYPE ("P"), .TYPE ("P"),
.BUFFERED_REQ (1), .BUFFERED_REQ (2),
.BUFFERED_RSP (1) .BUFFERED_RSP (2)
) mem_arb ( ) mem_arb (
.clk (clk), .clk (clk),
.reset (mem_arb_reset), .reset (mem_arb_reset),

79
hw/rtl/libs/VX_axi_adapter.v
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@@ -11,6 +11,9 @@ module VX_axi_adapter #(
localparam VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8), localparam VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8),
localparam AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8) localparam AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
) ( ) (
input wire clk,
input wire reset,
// Vortex request // Vortex request
input wire mem_req_valid, input wire mem_req_valid,
input wire mem_req_rw, input wire mem_req_rw,
@@ -26,29 +29,40 @@ module VX_axi_adapter #(
output wire [VX_TAG_WIDTH-1:0] mem_rsp_tag, output wire [VX_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_req_ready, output wire mem_req_ready,
// AXI write request // AXI write address channel
output wire m_axi_wvalid,
output wire m_axi_awvalid, output wire m_axi_awvalid,
output wire [AXI_TID_WIDTH-1:0] m_axi_awid, output wire [AXI_TID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen, output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize, output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst, output wire [1:0] m_axi_awburst,
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire m_axi_awlock,
output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb, output wire [3:0] m_axi_awcache,
input wire m_axi_wready, output wire [2:0] m_axi_awprot,
output wire [3:0] m_axi_awqos,
input wire m_axi_awready, input wire m_axi_awready,
// AXI read request // AXI write data channel
output wire m_axi_wvalid,
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb,
output wire m_axi_wlast,
input wire m_axi_wready,
// AXI read address channel
output wire m_axi_arvalid, output wire m_axi_arvalid,
output wire [AXI_TID_WIDTH-1:0] m_axi_arid, output wire [AXI_TID_WIDTH-1:0] m_axi_arid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen, output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize, output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst, output wire [1:0] m_axi_arburst,
output wire m_axi_arlock,
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire [3:0] m_axi_arqos,
input wire m_axi_arready, input wire m_axi_arready,
// AXI read response // AXI read data channel
input wire m_axi_rvalid, input wire m_axi_rvalid,
input wire [AXI_TID_WIDTH-1:0] m_axi_rid, input wire [AXI_TID_WIDTH-1:0] m_axi_rid,
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
@@ -59,30 +73,65 @@ module VX_axi_adapter #(
`STATIC_ASSERT((AXI_DATA_WIDTH == VX_DATA_WIDTH), ("invalid parameter")) `STATIC_ASSERT((AXI_DATA_WIDTH == VX_DATA_WIDTH), ("invalid parameter"))
`STATIC_ASSERT((AXI_TID_WIDTH == VX_TAG_WIDTH), ("invalid parameter")) `STATIC_ASSERT((AXI_TID_WIDTH == VX_TAG_WIDTH), ("invalid parameter"))
// AXI write channel reg awvalid_ack;
assign m_axi_wvalid = mem_req_valid & mem_req_rw; reg wvalid_ack;
assign m_axi_awvalid = mem_req_valid & mem_req_rw;
wire mem_req_fire = mem_req_valid && mem_req_ready;
always @(posedge clk) begin
if (reset) begin
awvalid_ack <= 0;
wvalid_ack <= 0;
end else begin
if (mem_req_fire) begin
awvalid_ack <= 0;
wvalid_ack <= 0;
end else begin
awvalid_ack <= m_axi_awvalid && m_axi_awready;
wvalid_ack <= m_axi_wvalid && m_axi_wready;
end
end
end
wire axi_write_ready = (m_axi_awready || awvalid_ack) && (m_axi_wready || wvalid_ack);
// AXI write address channel
assign m_axi_awvalid = mem_req_valid && mem_req_rw && !awvalid_ack;
assign m_axi_awid = mem_req_tag; assign m_axi_awid = mem_req_tag;
assign m_axi_awaddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE; assign m_axi_awaddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE;
assign m_axi_awlen = 8'b00000000; assign m_axi_awlen = 8'b00000000;
assign m_axi_awsize = 3'(AXSIZE); assign m_axi_awsize = 3'(AXSIZE);
assign m_axi_awburst = 2'b00; assign m_axi_awburst = 2'b00;
assign m_axi_awlock = 1'b0;
assign m_axi_awcache = 4'b0;
assign m_axi_awprot = 3'b0;
assign m_axi_awqos = 4'b0;
// AXI write data channel
assign m_axi_wvalid = mem_req_valid && mem_req_rw && !wvalid_ack;
assign m_axi_wdata = mem_req_data; assign m_axi_wdata = mem_req_data;
assign m_axi_wstrb = mem_req_byteen; assign m_axi_wstrb = mem_req_byteen;
assign m_axi_wlast = 1'b1;
// AXI read channel // AXI read address channel
assign m_axi_arvalid = mem_req_valid & ~mem_req_rw; assign m_axi_arvalid = mem_req_valid && !mem_req_rw;
assign m_axi_arid = mem_req_tag; assign m_axi_arid = mem_req_tag;
assign m_axi_araddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE; assign m_axi_araddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE;
assign m_axi_arlen = 8'b00000000; assign m_axi_arlen = 8'b00000000;
assign m_axi_arsize = 3'(AXSIZE); assign m_axi_arsize = 3'(AXSIZE);
assign m_axi_arburst = 2'b00; assign m_axi_arburst = 2'b00;
assign m_axi_rready = mem_rsp_ready; assign m_axi_arlock = 1'b0;
assign m_axi_arcache = 4'b0;
assign m_axi_arprot = 3'b0;
assign m_axi_arqos = 4'b0;
// Vortex inputs // AXI read data channel
assign mem_rsp_valid = m_axi_rvalid; assign mem_rsp_valid = m_axi_rvalid;
assign mem_rsp_tag = m_axi_rid; assign mem_rsp_tag = m_axi_rid;
assign mem_rsp_data = m_axi_rdata; assign mem_rsp_data = m_axi_rdata;
assign mem_req_ready = mem_req_rw ? (m_axi_awready && m_axi_wready) : m_axi_arready; assign m_axi_rready = mem_rsp_ready;
// Vortex request ack
assign mem_req_ready = mem_req_rw ? axi_write_ready : m_axi_arready;
endmodule endmodule