From f98e26e0f2d39f0906ab693fec365d3025b79970 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 11 Sep 2021 15:12:36 -0700 Subject: [PATCH 1/3] AXI interface update --- hw/rtl/Vortex_axi.v | 46 ++++++++++++++++++++++++++++--------- hw/rtl/afu/VX_avs_wrapper.v | 16 +++++-------- 2 files changed, 41 insertions(+), 21 deletions(-) diff --git a/hw/rtl/Vortex_axi.v b/hw/rtl/Vortex_axi.v index 48432203..06aa48b8 100644 --- a/hw/rtl/Vortex_axi.v +++ b/hw/rtl/Vortex_axi.v @@ -10,29 +10,40 @@ module Vortex_axi #( input wire clk, input wire reset, - // AXI write request - output wire m_axi_wvalid, + // AXI write address channel output wire m_axi_awvalid, output wire [AXI_TID_WIDTH-1:0] m_axi_awid, output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [7:0] m_axi_awlen, output wire [2:0] m_axi_awsize, - output wire [1:0] m_axi_awburst, + output wire [1:0] m_axi_awburst, + output wire m_axi_awlock, + output wire [3:0] m_axi_awcache, + output wire [2:0] m_axi_awprot, + output wire [3:0] m_axi_awqos, + input wire m_axi_awready, + + // AXI write data channel + output wire m_axi_wvalid, output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb, + output wire m_axi_wlast, input wire m_axi_wready, - input wire m_axi_awready, - // AXI read request + // AXI read address channel output wire m_axi_arvalid, output wire [AXI_TID_WIDTH-1:0] m_axi_arid, output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [7:0] m_axi_arlen, output wire [2:0] m_axi_arsize, - output wire [1:0] m_axi_arburst, + output wire [1:0] m_axi_arburst, + output wire m_axi_arlock, + output wire [3:0] m_axi_arcache, + output wire [2:0] m_axi_arprot, + output wire [3:0] m_axi_arqos, input wire m_axi_arready, - // AXI read response + // AXI read data channel input wire m_axi_rvalid, input wire [AXI_TID_WIDTH-1:0] m_axi_rid, input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, @@ -62,6 +73,9 @@ module Vortex_axi #( .AXI_ADDR_WIDTH (AXI_ADDR_WIDTH), .AXI_TID_WIDTH (AXI_TID_WIDTH) ) axi_adapter ( + .clk (clk), + .reset (reset), + .mem_req_valid (mem_req_valid), .mem_req_rw (mem_req_rw), .mem_req_byteen (mem_req_byteen), @@ -75,24 +89,34 @@ module Vortex_axi #( .mem_rsp_tag (mem_rsp_tag), .mem_rsp_ready (mem_rsp_ready), - .m_axi_wvalid (m_axi_wvalid), .m_axi_awvalid (m_axi_awvalid), .m_axi_awid (m_axi_awid), .m_axi_awaddr (m_axi_awaddr), .m_axi_awlen (m_axi_awlen), .m_axi_awsize (m_axi_awsize), - .m_axi_awburst (m_axi_awburst), + .m_axi_awburst (m_axi_awburst), + .m_axi_awlock (m_axi_awlock), + .m_axi_awcache (m_axi_awcache), + .m_axi_awprot (m_axi_awprot), + .m_axi_awqos (m_axi_awqos), + .m_axi_awready (m_axi_awready), + + .m_axi_wvalid (m_axi_wvalid), .m_axi_wdata (m_axi_wdata), .m_axi_wstrb (m_axi_wstrb), + .m_axi_wlast (m_axi_wlast), .m_axi_wready (m_axi_wready), - .m_axi_awready (m_axi_awready), .m_axi_arvalid (m_axi_arvalid), .m_axi_arid (m_axi_arid), .m_axi_araddr (m_axi_araddr), .m_axi_arlen (m_axi_arlen), .m_axi_arsize (m_axi_arsize), - .m_axi_arburst (m_axi_arburst), + .m_axi_arburst (m_axi_arburst), + .m_axi_arlock (m_axi_arlock), + .m_axi_arcache (m_axi_arcache), + .m_axi_arprot (m_axi_arprot), + .m_axi_arqos (m_axi_arqos), .m_axi_arready (m_axi_arready), .m_axi_rvalid (m_axi_rvalid), diff --git a/hw/rtl/afu/VX_avs_wrapper.v b/hw/rtl/afu/VX_avs_wrapper.v index 34431b91..fcfae197 100644 --- a/hw/rtl/afu/VX_avs_wrapper.v +++ b/hw/rtl/afu/VX_avs_wrapper.v @@ -42,7 +42,6 @@ module VX_avs_wrapper #( ); localparam BANK_ADDRW = `LOG2UP(AVS_BANKS); - localparam OUT_REG = (AVS_BANKS > 2); // Requests handling @@ -78,9 +77,8 @@ module VX_avs_wrapper #( `UNUSED_VAR (req_queue_size) VX_fifo_queue #( - .DATAW (REQ_TAG_WIDTH), - .SIZE (RD_QUEUE_SIZE), - .OUT_REG (!OUT_REG) + .DATAW (REQ_TAG_WIDTH), + .SIZE (RD_QUEUE_SIZE) ) rd_req_queue ( .clk (clk), .reset (reset), @@ -122,9 +120,8 @@ module VX_avs_wrapper #( for (genvar i = 0; i < AVS_BANKS; i++) begin VX_fifo_queue #( - .DATAW (AVS_DATA_WIDTH), - .SIZE (RD_QUEUE_SIZE), - .OUT_REG (!OUT_REG) + .DATAW (AVS_DATA_WIDTH), + .SIZE (RD_QUEUE_SIZE) ) rd_rsp_queue ( .clk (clk), .reset (reset), @@ -138,7 +135,7 @@ module VX_avs_wrapper #( `UNUSED_PIN (alm_full), `UNUSED_PIN (size) ); - end + end for (genvar i = 0; i < AVS_BANKS; i++) begin assign rsp_arb_valid_in[i] = !avs_rspq_empty[i]; @@ -149,8 +146,7 @@ module VX_avs_wrapper #( VX_stream_arbiter #( .NUM_REQS (AVS_BANKS), .DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH), - .TYPE ("R"), - .BUFFERED (OUT_REG ? 1 : 0) + .TYPE ("R") ) rsp_arb ( .clk (clk), .reset (reset), From 95287980afc457947faf61983b1a9ea01d8f71cc Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 11 Sep 2021 15:14:17 -0700 Subject: [PATCH 2/3] minor update --- hw/rtl/libs/VX_axi_adapter.v | 89 ++++++++++++++++++++++++++++-------- 1 file changed, 69 insertions(+), 20 deletions(-) diff --git a/hw/rtl/libs/VX_axi_adapter.v b/hw/rtl/libs/VX_axi_adapter.v index 6652401d..cf2be72a 100644 --- a/hw/rtl/libs/VX_axi_adapter.v +++ b/hw/rtl/libs/VX_axi_adapter.v @@ -11,6 +11,9 @@ module VX_axi_adapter #( localparam VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8), localparam AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8) ) ( + input wire clk, + input wire reset, + // Vortex request input wire mem_req_valid, input wire mem_req_rw, @@ -26,29 +29,40 @@ module VX_axi_adapter #( output wire [VX_TAG_WIDTH-1:0] mem_rsp_tag, output wire mem_req_ready, - // AXI write request - output wire m_axi_wvalid, + // AXI write address channel output wire m_axi_awvalid, output wire [AXI_TID_WIDTH-1:0] m_axi_awid, output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, output wire [7:0] m_axi_awlen, output wire [2:0] m_axi_awsize, - output wire [1:0] m_axi_awburst, + output wire [1:0] m_axi_awburst, + output wire m_axi_awlock, + output wire [3:0] m_axi_awcache, + output wire [2:0] m_axi_awprot, + output wire [3:0] m_axi_awqos, + input wire m_axi_awready, + + // AXI write data channel + output wire m_axi_wvalid, output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb, + output wire m_axi_wlast, input wire m_axi_wready, - input wire m_axi_awready, - // AXI read request + // AXI read address channel output wire m_axi_arvalid, output wire [AXI_TID_WIDTH-1:0] m_axi_arid, output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr, output wire [7:0] m_axi_arlen, output wire [2:0] m_axi_arsize, output wire [1:0] m_axi_arburst, + output wire m_axi_arlock, + output wire [3:0] m_axi_arcache, + output wire [2:0] m_axi_arprot, + output wire [3:0] m_axi_arqos, input wire m_axi_arready, - // AXI read response + // AXI read data channel input wire m_axi_rvalid, input wire [AXI_TID_WIDTH-1:0] m_axi_rid, input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata, @@ -59,30 +73,65 @@ module VX_axi_adapter #( `STATIC_ASSERT((AXI_DATA_WIDTH == VX_DATA_WIDTH), ("invalid parameter")) `STATIC_ASSERT((AXI_TID_WIDTH == VX_TAG_WIDTH), ("invalid parameter")) - // AXI write channel - assign m_axi_wvalid = mem_req_valid & mem_req_rw; - assign m_axi_awvalid = mem_req_valid & mem_req_rw; + reg awvalid_ack; + reg wvalid_ack; + + wire mem_req_fire = mem_req_valid && mem_req_ready; + + always @(posedge clk) begin + if (reset) begin + awvalid_ack <= 0; + wvalid_ack <= 0; + end else begin + if (mem_req_fire) begin + awvalid_ack <= 0; + wvalid_ack <= 0; + end else begin + awvalid_ack <= m_axi_awvalid && m_axi_awready; + wvalid_ack <= m_axi_wvalid && m_axi_wready; + end + end + end + + wire axi_write_ready = (m_axi_awready || awvalid_ack) && (m_axi_wready || wvalid_ack); + + // AXI write address channel + assign m_axi_awvalid = mem_req_valid && mem_req_rw && !awvalid_ack; assign m_axi_awid = mem_req_tag; - assign m_axi_awaddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE; - assign m_axi_awlen = 8'b00000000; + assign m_axi_awaddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE; + assign m_axi_awlen = 8'b00000000; assign m_axi_awsize = 3'(AXSIZE); - assign m_axi_awburst = 2'b00; + assign m_axi_awburst = 2'b00; + assign m_axi_awlock = 1'b0; + assign m_axi_awcache = 4'b0; + assign m_axi_awprot = 3'b0; + assign m_axi_awqos = 4'b0; + + // AXI write data channel + assign m_axi_wvalid = mem_req_valid && mem_req_rw && !wvalid_ack; assign m_axi_wdata = mem_req_data; assign m_axi_wstrb = mem_req_byteen; - - // AXI read channel - assign m_axi_arvalid = mem_req_valid & ~mem_req_rw; + assign m_axi_wlast = 1'b1; + + // AXI read address channel + assign m_axi_arvalid = mem_req_valid && !mem_req_rw; assign m_axi_arid = mem_req_tag; - assign m_axi_araddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE; + assign m_axi_araddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE; assign m_axi_arlen = 8'b00000000; assign m_axi_arsize = 3'(AXSIZE); - assign m_axi_arburst = 2'b00; - assign m_axi_rready = mem_rsp_ready; + assign m_axi_arburst = 2'b00; + assign m_axi_arlock = 1'b0; + assign m_axi_arcache = 4'b0; + assign m_axi_arprot = 3'b0; + assign m_axi_arqos = 4'b0; - // Vortex inputs + // AXI read data channel assign mem_rsp_valid = m_axi_rvalid; assign mem_rsp_tag = m_axi_rid; assign mem_rsp_data = m_axi_rdata; - assign mem_req_ready = mem_req_rw ? (m_axi_awready && m_axi_wready) : m_axi_arready; + assign m_axi_rready = mem_rsp_ready; + + // Vortex request ack + assign mem_req_ready = mem_req_rw ? axi_write_ready : m_axi_arready; endmodule \ No newline at end of file From 182811697e9f5cc8e8762dcd79e1294bfc025a1a Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Sat, 11 Sep 2021 15:14:55 -0700 Subject: [PATCH 3/3] minor update --- hw/rtl/afu/vortex_afu.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index 1ef81393..1656ed17 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -520,8 +520,8 @@ VX_mem_arb #( .ADDR_WIDTH (LMEM_ADDR_WIDTH), .TAG_IN_WIDTH (AVS_REQ_TAGW), .TYPE ("P"), - .BUFFERED_REQ (1), - .BUFFERED_RSP (1) + .BUFFERED_REQ (2), + .BUFFERED_RSP (2) ) mem_arb ( .clk (clk), .reset (mem_arb_reset),