pipeline refactoring - fmax >= 222 mhz

2020-08-14 21:50:14 -07:00
parent 71a46d04b9
commit 6c12391338
107 changed files with 1392 additions and 1239 deletions
--- a/hw/rtl/cache/VX_snp_rsp_arb.v
+++ b/hw/rtl/cache/VX_snp_rsp_arb.v
@@ -34,8 +34,7 @@ module VX_snp_rsp_arb #(
    assign snp_rsp_valid = fsq_valid;
    assign snp_rsp_tag   = per_bank_snp_rsp_tag[fsq_bank];

-    genvar i;
-    for (i = 0; i < NUM_BANKS; i++) begin
+    for (genvar i = 0; i < NUM_BANKS; i++) begin
        assign per_bank_snp_rsp_ready[i] = snp_rsp_ready && (fsq_bank == `BANK_BITS'(i));
    end