41 lines
1.2 KiB
Verilog
41 lines
1.2 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_snp_rsp_arb #(
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parameter NUM_BANKS = 0,
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parameter BANK_LINE_SIZE = 0,
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parameter SNP_REQ_TAG_WIDTH = 0
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) (
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input wire clk,
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input wire reset,
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input wire [NUM_BANKS-1:0] per_bank_snp_rsp_valid,
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input wire [NUM_BANKS-1:0][SNP_REQ_TAG_WIDTH-1:0] per_bank_snp_rsp_tag,
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output wire [NUM_BANKS-1:0] per_bank_snp_rsp_ready,
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output wire snp_rsp_valid,
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output wire [SNP_REQ_TAG_WIDTH-1:0] snp_rsp_tag,
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input wire snp_rsp_ready
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);
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wire [`BANK_BITS-1:0] fsq_bank;
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wire fsq_valid;
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VX_fixed_arbiter #(
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.N(NUM_BANKS)
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) sel_ffsq (
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.clk (clk),
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.reset (reset),
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.requests (per_bank_snp_rsp_valid),
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.grant_index (fsq_bank),
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.grant_valid (fsq_valid),
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`UNUSED_PIN (grant_onehot)
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);
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assign snp_rsp_valid = fsq_valid;
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assign snp_rsp_tag = per_bank_snp_rsp_tag[fsq_bank];
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for (genvar i = 0; i < NUM_BANKS; i++) begin
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assign per_bank_snp_rsp_ready[i] = snp_rsp_ready && (fsq_bank == `BANK_BITS'(i));
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end
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endmodule |