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SOC only 2 errors

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This commit is contained in:
felsabbagh3
2020-03-30 21:28:40 -07:00
parent 88f2ad53d0
commit 66a837b0df
2 changed files with 6 additions and 6 deletions
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4
rtl/VX_cache/VX_tag_data_access.v
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@@ -238,7 +238,7 @@ module VX_tag_data_access
wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000))); wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000)));
wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e; wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e && !is_snp_st1e;
wire force_write = real_writefill; wire force_write = real_writefill;
wire[`DBANK_LINE_SIZE_RNG][3:0] we; wire[`DBANK_LINE_SIZE_RNG][3:0] we;
@@ -278,7 +278,7 @@ module VX_tag_data_access
wire tags_mismatch = writeaddr_tag != use_read_tag_st1e; wire tags_mismatch = writeaddr_tag != use_read_tag_st1e;
wire tags_match = writeaddr_tag == use_read_tag_st1e; wire tags_match = writeaddr_tag == use_read_tag_st1e;
wire snoop_hit = valid_req_st1e && is_snp_st1e && tags_match; wire snoop_hit = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match;
wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e; wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e;
wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && tags_mismatch; wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && tags_mismatch;

8
rtl/simulate/simulator.cpp
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@@ -345,14 +345,14 @@ void Simulator::send_snoops(uint32_t mem_addr, uint32_t size) {
void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) { void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
// send snoops for L1 flush // send snoops for L1 flush
this->send_snoops(mem_addr, size); this->send_snoops(mem_addr, size);
this->wait(PIPELINE_FLUSH_LATENCY);
#if NUMBER_CORES != 1 // #if NUMBER_CORES != 1
// send snoops for L2 flush // send snoops for L2 flush
this->send_snoops(mem_addr, size); this->send_snoops(mem_addr, size);
#endif
// wait some cycles to ensure that the request has committed
this->wait(PIPELINE_FLUSH_LATENCY); this->wait(PIPELINE_FLUSH_LATENCY);
// #endif
} }
bool Simulator::run() { bool Simulator::run() {