From 66a837b0dfcb768a1b22037bcd3c455e1ec4dc04 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Mon, 30 Mar 2020 21:28:40 -0700 Subject: [PATCH] SOC only 2 errors --- rtl/VX_cache/VX_tag_data_access.v | 4 ++-- rtl/simulate/simulator.cpp | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/rtl/VX_cache/VX_tag_data_access.v b/rtl/VX_cache/VX_tag_data_access.v index 1e8567d3..471a0956 100644 --- a/rtl/VX_cache/VX_tag_data_access.v +++ b/rtl/VX_cache/VX_tag_data_access.v @@ -238,7 +238,7 @@ module VX_tag_data_access wire[3:0] sb_mask = (b0 ? 4'b0001 : (b1 ? 4'b0010 : (b2 ? 4'b0100 : 4'b1000))); wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100); - wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e; + wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e && !is_snp_st1e; wire force_write = real_writefill; wire[`DBANK_LINE_SIZE_RNG][3:0] we; @@ -278,7 +278,7 @@ module VX_tag_data_access wire tags_mismatch = writeaddr_tag != use_read_tag_st1e; wire tags_match = writeaddr_tag == use_read_tag_st1e; - wire snoop_hit = valid_req_st1e && is_snp_st1e && tags_match; + wire snoop_hit = valid_req_st1e && is_snp_st1e && use_read_valid_st1e && tags_match; wire req_invalid = valid_req_st1e && !is_snp_st1e && !use_read_valid_st1e && !writefill_st1e; wire req_miss = valid_req_st1e && !is_snp_st1e && use_read_valid_st1e && !writefill_st1e && tags_mismatch; diff --git a/rtl/simulate/simulator.cpp b/rtl/simulate/simulator.cpp index d88065eb..8bd2e4bf 100644 --- a/rtl/simulate/simulator.cpp +++ b/rtl/simulate/simulator.cpp @@ -345,14 +345,14 @@ void Simulator::send_snoops(uint32_t mem_addr, uint32_t size) { void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) { // send snoops for L1 flush this->send_snoops(mem_addr, size); + this->wait(PIPELINE_FLUSH_LATENCY); -#if NUMBER_CORES != 1 +// #if NUMBER_CORES != 1 // send snoops for L2 flush this->send_snoops(mem_addr, size); -#endif - - // wait some cycles to ensure that the request has committed this->wait(PIPELINE_FLUSH_LATENCY); +// #endif + } bool Simulator::run() {