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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 07:24:20 -04:00
parent 58850a2fe8
commit 62c1c3fdbb
8 changed files with 145 additions and 145 deletions
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114
hw/rtl/VX_dmem_controller.v
View File

@@ -30,7 +30,7 @@ module VX_dmem_controller (
VX_gpu_dcache_rsp_if #(.NUM_REQUESTS(`DNUM_REQUESTS)) dcache_rsp_dcache_if();
wire to_shm = dcache_req_if.core_req_addr[0][31:24] == 8'hFF;
wire dcache_wants_wb = (|dcache_rsp_dcache_if.core_wb_valid);
wire dcache_wants_wb = (|dcache_rsp_dcache_if.core_rsp_valid);
// Dcache Request
assign dcache_req_dcache_if.core_req_valid = dcache_req_if.core_req_valid & {`NUM_THREADS{~to_shm}};
@@ -43,7 +43,7 @@ module VX_dmem_controller (
assign dcache_req_dcache_if.core_req_warp_num = dcache_req_if.core_req_warp_num;
assign dcache_req_dcache_if.core_req_pc = dcache_req_if.core_req_pc;
assign dcache_rsp_dcache_if.core_no_wb_slot = dcache_rsp_if.core_no_wb_slot;
assign dcache_rsp_dcache_if.core_rsp_ready = dcache_rsp_if.core_rsp_ready;
// Shared Memory Request
assign dcache_req_smem_if.core_req_valid = dcache_req_if.core_req_valid & {`NUM_THREADS{to_shm}};
@@ -56,15 +56,15 @@ module VX_dmem_controller (
assign dcache_req_smem_if.core_req_warp_num = dcache_req_if.core_req_warp_num;
assign dcache_req_smem_if.core_req_pc = dcache_req_if.core_req_pc;
assign dcache_rsp_smem_if.core_no_wb_slot = dcache_rsp_if.core_no_wb_slot || dcache_wants_wb;
assign dcache_rsp_smem_if.core_rsp_ready = dcache_rsp_if.core_rsp_ready && ~dcache_wants_wb;
// Dcache Response
assign dcache_rsp_if.core_wb_valid = dcache_wants_wb ? dcache_rsp_dcache_if.core_wb_valid : dcache_rsp_smem_if.core_wb_valid;
assign dcache_rsp_if.core_wb_req_rd = dcache_wants_wb ? dcache_rsp_dcache_if.core_wb_req_rd : dcache_rsp_smem_if.core_wb_req_rd;
assign dcache_rsp_if.core_wb_req_wb = dcache_wants_wb ? dcache_rsp_dcache_if.core_wb_req_wb : dcache_rsp_smem_if.core_wb_req_wb;
assign dcache_rsp_if.core_wb_pc = dcache_wants_wb ? dcache_rsp_dcache_if.core_wb_pc : dcache_rsp_smem_if.core_wb_pc;
assign dcache_rsp_if.core_wb_readdata = dcache_wants_wb ? dcache_rsp_dcache_if.core_wb_readdata : dcache_rsp_smem_if.core_wb_readdata;
assign dcache_rsp_if.core_wb_warp_num = dcache_wants_wb ? dcache_rsp_dcache_if.core_wb_warp_num : dcache_rsp_smem_if.core_wb_warp_num;
assign dcache_rsp_if.core_rsp_valid = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_valid : dcache_rsp_smem_if.core_rsp_valid;
assign dcache_rsp_if.core_rsp_req_rd = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_req_rd : dcache_rsp_smem_if.core_rsp_req_rd;
assign dcache_rsp_if.core_rsp_req_wb = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_req_wb : dcache_rsp_smem_if.core_rsp_req_wb;
assign dcache_rsp_if.core_rsp_pc = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_pc : dcache_rsp_smem_if.core_rsp_pc;
assign dcache_rsp_if.core_rsp_readdata = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_readdata : dcache_rsp_smem_if.core_rsp_readdata;
assign dcache_rsp_if.core_rsp_warp_num = dcache_wants_wb ? dcache_rsp_dcache_if.core_rsp_warp_num : dcache_rsp_smem_if.core_rsp_warp_num;
assign dcache_req_if.core_req_ready = to_shm ? dcache_req_smem_if.core_req_ready : dcache_req_dcache_if.core_req_ready;
@@ -93,35 +93,35 @@ module VX_dmem_controller (
.FILL_INVALIDAOR_SIZE (`SFILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`SSIMULATED_DRAM_LATENCY_CYCLES)
) gpu_smem (
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
// Core req
.core_req_valid (dcache_req_smem_if.core_req_valid),
.core_req_mem_read (dcache_req_smem_if.core_req_mem_read),
.core_req_mem_write(dcache_req_smem_if.core_req_mem_write),
.core_req_addr (dcache_req_smem_if.core_req_addr),
.core_req_writedata(dcache_req_smem_if.core_req_writedata),
.core_req_rd (dcache_req_smem_if.core_req_rd),
.core_req_wb (dcache_req_smem_if.core_req_wb),
.core_req_warp_num (dcache_req_smem_if.core_req_warp_num),
.core_req_pc (dcache_req_smem_if.core_req_pc),
.core_req_valid (dcache_req_smem_if.core_req_valid),
.core_req_mem_read (dcache_req_smem_if.core_req_mem_read),
.core_req_mem_write (dcache_req_smem_if.core_req_mem_write),
.core_req_addr (dcache_req_smem_if.core_req_addr),
.core_req_writedata (dcache_req_smem_if.core_req_writedata),
.core_req_rd (dcache_req_smem_if.core_req_rd),
.core_req_wb (dcache_req_smem_if.core_req_wb),
.core_req_warp_num (dcache_req_smem_if.core_req_warp_num),
.core_req_pc (dcache_req_smem_if.core_req_pc),
// Can submit core Req
.core_req_ready (dcache_req_smem_if.core_req_ready),
.core_req_ready (dcache_req_smem_if.core_req_ready),
// Core Cache Can't WB
.core_no_wb_slot (dcache_rsp_smem_if.core_no_wb_slot),
.core_rsp_ready (dcache_rsp_smem_if.core_rsp_ready),
// Cache CWB
.core_wb_valid (dcache_rsp_smem_if.core_wb_valid),
.core_wb_req_rd (dcache_rsp_smem_if.core_wb_req_rd),
.core_wb_req_wb (dcache_rsp_smem_if.core_wb_req_wb),
.core_wb_warp_num (dcache_rsp_smem_if.core_wb_warp_num),
.core_wb_readdata (dcache_rsp_smem_if.core_wb_readdata),
.core_wb_pc (dcache_rsp_smem_if.core_wb_pc),
.core_rsp_valid (dcache_rsp_smem_if.core_rsp_valid),
.core_rsp_req_rd (dcache_rsp_smem_if.core_rsp_req_rd),
.core_rsp_req_wb (dcache_rsp_smem_if.core_rsp_req_wb),
.core_rsp_warp_num (dcache_rsp_smem_if.core_rsp_warp_num),
.core_rsp_readdata (dcache_rsp_smem_if.core_rsp_readdata),
.core_rsp_pc (dcache_rsp_smem_if.core_rsp_pc),
`IGNORE_WARNINGS_BEGIN
.core_wb_address (),
.core_rsp_address (),
`IGNORE_WARNINGS_END
// DRAM response
@@ -176,35 +176,35 @@ module VX_dmem_controller (
.FILL_INVALIDAOR_SIZE (`DFILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(`DSIMULATED_DRAM_LATENCY_CYCLES)
) gpu_dcache (
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
// Core req
.core_req_valid (dcache_req_dcache_if.core_req_valid),
.core_req_mem_read (dcache_req_dcache_if.core_req_mem_read),
.core_req_mem_write(dcache_req_dcache_if.core_req_mem_write),
.core_req_addr (dcache_req_dcache_if.core_req_addr),
.core_req_writedata(dcache_req_dcache_if.core_req_writedata),
.core_req_rd (dcache_req_dcache_if.core_req_rd),
.core_req_wb (dcache_req_dcache_if.core_req_wb),
.core_req_warp_num (dcache_req_dcache_if.core_req_warp_num),
.core_req_pc (dcache_req_dcache_if.core_req_pc),
.core_req_valid (dcache_req_dcache_if.core_req_valid),
.core_req_mem_read (dcache_req_dcache_if.core_req_mem_read),
.core_req_mem_write (dcache_req_dcache_if.core_req_mem_write),
.core_req_addr (dcache_req_dcache_if.core_req_addr),
.core_req_writedata (dcache_req_dcache_if.core_req_writedata),
.core_req_rd (dcache_req_dcache_if.core_req_rd),
.core_req_wb (dcache_req_dcache_if.core_req_wb),
.core_req_warp_num (dcache_req_dcache_if.core_req_warp_num),
.core_req_pc (dcache_req_dcache_if.core_req_pc),
// Can submit core Req
.core_req_ready (dcache_req_dcache_if.core_req_ready),
.core_req_ready (dcache_req_dcache_if.core_req_ready),
// Core Cache Can't WB
.core_no_wb_slot (dcache_rsp_dcache_if.core_no_wb_slot),
.core_rsp_ready (dcache_rsp_dcache_if.core_rsp_ready),
// Cache CWB
.core_wb_valid (dcache_rsp_dcache_if.core_wb_valid),
.core_wb_req_rd (dcache_rsp_dcache_if.core_wb_req_rd),
.core_wb_req_wb (dcache_rsp_dcache_if.core_wb_req_wb),
.core_wb_warp_num (dcache_rsp_dcache_if.core_wb_warp_num),
.core_wb_readdata (dcache_rsp_dcache_if.core_wb_readdata),
.core_wb_pc (dcache_rsp_dcache_if.core_wb_pc),
.core_rsp_valid (dcache_rsp_dcache_if.core_rsp_valid),
.core_rsp_req_rd (dcache_rsp_dcache_if.core_rsp_req_rd),
.core_rsp_req_wb (dcache_rsp_dcache_if.core_rsp_req_wb),
.core_rsp_warp_num (dcache_rsp_dcache_if.core_rsp_warp_num),
.core_rsp_readdata (dcache_rsp_dcache_if.core_rsp_readdata),
.core_rsp_pc (dcache_rsp_dcache_if.core_rsp_pc),
`IGNORE_WARNINGS_BEGIN
.core_wb_address (),
.core_rsp_address (),
`IGNORE_WARNINGS_END
// DRAM response
@@ -275,17 +275,17 @@ module VX_dmem_controller (
.core_req_ready (icache_req_if.core_req_ready),
// Core Cache Can't WB
.core_no_wb_slot (icache_rsp_if.core_no_wb_slot),
.core_rsp_ready (icache_rsp_if.core_rsp_ready),
// Cache CWB
.core_wb_valid (icache_rsp_if.core_wb_valid),
.core_wb_req_rd (icache_rsp_if.core_wb_req_rd),
.core_wb_req_wb (icache_rsp_if.core_wb_req_wb),
.core_wb_warp_num (icache_rsp_if.core_wb_warp_num),
.core_wb_readdata (icache_rsp_if.core_wb_readdata),
.core_wb_pc (icache_rsp_if.core_wb_pc),
.core_rsp_valid (icache_rsp_if.core_rsp_valid),
.core_rsp_req_rd (icache_rsp_if.core_rsp_req_rd),
.core_rsp_req_wb (icache_rsp_if.core_rsp_req_wb),
.core_rsp_warp_num (icache_rsp_if.core_rsp_warp_num),
.core_rsp_readdata (icache_rsp_if.core_rsp_readdata),
.core_rsp_pc (icache_rsp_if.core_rsp_pc),
`IGNORE_WARNINGS_BEGIN
.core_wb_address (),
.core_rsp_address (),
`IGNORE_WARNINGS_END
// DRAM response

10
hw/rtl/VX_icache_stage.v
View File

@@ -29,11 +29,11 @@ module VX_icache_stage (
assign icache_req_if.core_req_warp_num = fe_inst_meta_fi.warp_num;
assign icache_req_if.core_req_pc = fe_inst_meta_fi.inst_pc;
assign fe_inst_meta_id.instruction = icache_rsp_if.core_wb_readdata[0][31:0];
assign fe_inst_meta_id.inst_pc = icache_rsp_if.core_wb_pc[0];
assign fe_inst_meta_id.warp_num = icache_rsp_if.core_wb_warp_num;
assign fe_inst_meta_id.instruction = icache_rsp_if.core_rsp_readdata[0][31:0];
assign fe_inst_meta_id.inst_pc = icache_rsp_if.core_rsp_pc[0];
assign fe_inst_meta_id.warp_num = icache_rsp_if.core_rsp_warp_num;
assign fe_inst_meta_id.valid = icache_rsp_if.core_wb_valid ? threads_active[icache_rsp_if.core_wb_warp_num] : 0;
assign fe_inst_meta_id.valid = icache_rsp_if.core_rsp_valid ? threads_active[icache_rsp_if.core_rsp_warp_num] : 0;
assign icache_stage_wid = fe_inst_meta_id.warp_num;
assign icache_stage_valids = fe_inst_meta_id.valid & {`NUM_THREADS{!icache_stage_delay}};
@@ -42,7 +42,7 @@ module VX_icache_stage (
assign icache_stage_delay = ~icache_req_if.core_req_ready;
// Core can't accept response
assign icache_rsp_if.core_no_wb_slot = total_freeze;
assign icache_rsp_if.core_rsp_ready = ~total_freeze;
integer curr_w;
always @(posedge clk) begin

16
hw/rtl/VX_lsu.v
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@@ -56,17 +56,17 @@ module VX_lsu (
assign dcache_req_if.core_req_pc = use_pc;
// Core can't accept response
assign dcache_rsp_if.core_no_wb_slot = no_slot_mem;
assign dcache_rsp_if.core_rsp_ready = ~no_slot_mem;
// Cache can't accept request
assign out_delay = ~dcache_req_if.core_req_ready;
// Core Response
assign mem_wb_if.rd = dcache_rsp_if.core_wb_req_rd;
assign mem_wb_if.wb = dcache_rsp_if.core_wb_req_wb;
assign mem_wb_if.wb_valid = dcache_rsp_if.core_wb_valid;
assign mem_wb_if.wb_warp_num = dcache_rsp_if.core_wb_warp_num;
assign mem_wb_if.loaded_data = dcache_rsp_if.core_wb_readdata;
assign mem_wb_if.rd = dcache_rsp_if.core_rsp_req_rd;
assign mem_wb_if.wb = dcache_rsp_if.core_rsp_req_wb;
assign mem_wb_if.wb_valid = dcache_rsp_if.core_rsp_valid;
assign mem_wb_if.wb_warp_num = dcache_rsp_if.core_rsp_warp_num;
assign mem_wb_if.loaded_data = dcache_rsp_if.core_rsp_readdata;
wire[(`LOG2UP(`NUM_THREADS))-1:0] use_pc_index;
@@ -75,12 +75,12 @@ module VX_lsu (
`DEBUG_END
VX_generic_priority_encoder #(.N(`NUM_THREADS)) pick_first_pc(
.valids(dcache_rsp_if.core_wb_valid),
.valids(dcache_rsp_if.core_rsp_valid),
.index (use_pc_index),
.found (found)
);
assign mem_wb_if.mem_wb_pc = dcache_rsp_if.core_wb_pc[use_pc_index];
assign mem_wb_if.mem_wb_pc = dcache_rsp_if.core_rsp_pc[use_pc_index];
endmodule // Memory

22
hw/rtl/Vortex_Cluster.v
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@@ -126,7 +126,7 @@ module Vortex_Cluster #(
wire[`L2NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l2c_core_req_data;
wire[`L2NUM_REQUESTS-1:0][1:0] l2c_core_req_wb;
wire[`L2NUM_REQUESTS-1:0] l2c_core_no_wb_slot;
wire[`L2NUM_REQUESTS-1:0] l2c_core_rsp_ready;
wire[`L2NUM_REQUESTS-1:0] l2c_wb;
wire[`L2NUM_REQUESTS-1:0] [31:0] l2c_wb_addr;
@@ -166,8 +166,8 @@ module Vortex_Cluster #(
assign l2c_core_req_data [l2c_curr_core+1] = per_core_I_dram_req_data[(l2c_curr_core/2)];
// Core can't accept Response
assign l2c_core_no_wb_slot [l2c_curr_core] = ~per_core_dram_rsp_ready [(l2c_curr_core/2)];
assign l2c_core_no_wb_slot [l2c_curr_core+1] = ~per_core_I_dram_rsp_ready[(l2c_curr_core/2)];
assign l2c_core_rsp_ready [l2c_curr_core] = per_core_dram_rsp_ready [(l2c_curr_core/2)];
assign l2c_core_rsp_ready [l2c_curr_core+1] = per_core_I_dram_rsp_ready[(l2c_curr_core/2)];
// Cache Fill Response
assign per_core_dram_rsp_valid [(l2c_curr_core/2)] = l2c_wb[l2c_curr_core];
@@ -221,18 +221,18 @@ module Vortex_Cluster #(
.core_req_ready (l2c_core_req_ready),
// Core can't accept L2 Request
.core_no_wb_slot (|l2c_core_no_wb_slot),
.core_rsp_ready (|l2c_core_rsp_ready),
// Core Writeback
.core_wb_valid (l2c_wb),
.core_rsp_valid (l2c_wb),
`IGNORE_WARNINGS_BEGIN
.core_wb_req_rd (),
.core_wb_req_wb (),
.core_wb_warp_num (),
.core_wb_pc (),
.core_rsp_req_rd (),
.core_rsp_req_wb (),
.core_rsp_warp_num (),
.core_rsp_pc (),
`IGNORE_WARNINGS_END
.core_wb_readdata ({l2c_wb_data}),
.core_wb_address (l2c_wb_addr),
.core_rsp_readdata ({l2c_wb_data}),
.core_rsp_address (l2c_wb_addr),
// L2 Cache DRAM Fill response
.dram_rsp_valid (dram_rsp_valid),

20
hw/rtl/Vortex_Socket.v
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@@ -148,7 +148,7 @@ module Vortex_Socket (
wire[`L3NUM_REQUESTS-1:0][`IBANK_LINE_WORDS-1:0][31:0] l3c_core_req_data;
wire[`L3NUM_REQUESTS-1:0][1:0] l3c_core_req_wb;
wire[`L3NUM_REQUESTS-1:0] l3c_core_no_wb_slot;
wire[`L3NUM_REQUESTS-1:0] l3c_core_rsp_ready;
wire[`L3NUM_REQUESTS-1:0] l3c_wb;
wire[`L3NUM_REQUESTS-1:0] [31:0] l3c_wb_addr;
@@ -174,7 +174,7 @@ module Vortex_Socket (
assign l3c_core_req_data [l3c_curr_cluster] = per_cluster_dram_req_data [l3c_curr_cluster];
// Core can't accept Response
assign l3c_core_no_wb_slot [l3c_curr_cluster] = ~per_cluster_dram_rsp_ready[l3c_curr_cluster];
assign l3c_core_rsp_ready [l3c_curr_cluster] = per_cluster_dram_rsp_ready[l3c_curr_cluster];
// Cache Fill Response
assign per_cluster_dram_rsp_valid [l3c_curr_cluster] = l3c_wb [l3c_curr_cluster];
@@ -222,18 +222,18 @@ module Vortex_Socket (
.core_req_ready (l3c_core_req_ready),
// Core can't accept L2 Request
.core_no_wb_slot (|l3c_core_no_wb_slot),
.core_rsp_ready (|l3c_core_rsp_ready),
// Core Writeback
.core_wb_valid (l3c_wb),
.core_rsp_valid (l3c_wb),
`IGNORE_WARNINGS_BEGIN
.core_wb_req_rd (),
.core_wb_req_wb (),
.core_wb_warp_num (),
.core_wb_pc (),
.core_rsp_req_rd (),
.core_rsp_req_wb (),
.core_rsp_warp_num (),
.core_rsp_pc (),
`IGNORE_WARNINGS_END
.core_wb_readdata ({l3c_wb_data}),
.core_wb_address (l3c_wb_addr),
.core_rsp_readdata ({l3c_wb_data}),
.core_rsp_address (l3c_wb_addr),
// L2 Cache DRAM Fill response
.dram_rsp_valid (dram_rsp_valid),

34
hw/rtl/generic_cache/VX_cache.v
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@@ -68,16 +68,16 @@ module VX_cache #(
// Core response
output wire [NUM_REQUESTS-1:0] core_wb_valid,
output wire [4:0] core_wb_req_rd,
output wire [1:0] core_wb_req_wb,
output wire [NUM_REQUESTS-1:0][31:0] core_wb_address,
output wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata,
input wire core_no_wb_slot,
output wire [NUM_REQUESTS-1:0] core_rsp_valid,
output wire [4:0] core_rsp_req_rd,
output wire [1:0] core_rsp_req_wb,
output wire [NUM_REQUESTS-1:0][31:0] core_rsp_address,
output wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_readdata,
input wire core_rsp_ready,
// Core response meta data
output wire [`NW_BITS-1:0] core_wb_warp_num,
output wire [NUM_REQUESTS-1:0][31:0] core_wb_pc,
output wire [`NW_BITS-1:0] core_rsp_warp_num,
output wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc,
// DRAM request
output wire dram_req_read,
@@ -217,7 +217,7 @@ module VX_cache #(
.LLVQ_SIZE (LLVQ_SIZE),
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
) cache_core_wb_sel_merge (
) cache_core_rsp_sel_merge (
.per_bank_wb_valid (per_bank_wb_valid),
.per_bank_wb_tid (per_bank_wb_tid),
.per_bank_wb_rd (per_bank_wb_rd),
@@ -228,14 +228,14 @@ module VX_cache #(
.per_bank_wb_pop (per_bank_wb_pop),
.per_bank_wb_address (per_bank_wb_address),
.core_no_wb_slot (core_no_wb_slot),
.core_wb_valid (core_wb_valid),
.core_wb_req_rd (core_wb_req_rd),
.core_wb_req_wb (core_wb_req_wb),
.core_wb_warp_num (core_wb_warp_num),
.core_wb_readdata (core_wb_readdata),
.core_wb_address (core_wb_address),
.core_wb_pc (core_wb_pc)
.core_rsp_ready (core_rsp_ready),
.core_rsp_valid (core_rsp_valid),
.core_rsp_req_rd (core_rsp_req_rd),
.core_rsp_req_wb (core_rsp_req_wb),
.core_rsp_warp_num (core_rsp_warp_num),
.core_rsp_readdata (core_rsp_readdata),
.core_rsp_address (core_rsp_address),
.core_rsp_pc (core_rsp_pc)
);
// Snoop Forward Logic

60
hw/rtl/generic_cache/VX_cache_wb_sel_merge.v
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@@ -54,18 +54,18 @@ module VX_cache_wb_sel_merge #(
output wire [NUM_BANKS-1:0] per_bank_wb_pop,
// Core Writeback
input wire core_no_wb_slot,
output reg [NUM_REQUESTS-1:0] core_wb_valid,
output reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata,
output reg [NUM_REQUESTS-1:0][31:0] core_wb_pc,
output wire [4:0] core_wb_req_rd,
output wire [1:0] core_wb_req_wb,
output wire [`NW_BITS-1:0] core_wb_warp_num,
output reg [NUM_REQUESTS-1:0][31:0] core_wb_address
input wire core_rsp_ready,
output reg [NUM_REQUESTS-1:0] core_rsp_valid,
output reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_readdata,
output reg [NUM_REQUESTS-1:0][31:0] core_rsp_pc,
output wire [4:0] core_rsp_req_rd,
output wire [1:0] core_rsp_req_wb,
output wire [`NW_BITS-1:0] core_rsp_warp_num,
output reg [NUM_REQUESTS-1:0][31:0] core_rsp_address
);
reg [NUM_BANKS-1:0] per_bank_wb_pop_unqual;
assign per_bank_wb_pop = per_bank_wb_pop_unqual & {NUM_BANKS{~core_no_wb_slot}};
assign per_bank_wb_pop = per_bank_wb_pop_unqual & {NUM_BANKS{core_rsp_ready}};
// wire[NUM_BANKS-1:0] bank_wants_wb;
// genvar curr_bank;
@@ -86,47 +86,47 @@ module VX_cache_wb_sel_merge #(
.found (found_bank)
);
assign core_wb_req_rd = per_bank_wb_rd[main_bank_index];
assign core_wb_req_wb = per_bank_wb_wb[main_bank_index];
assign core_wb_warp_num = per_bank_wb_warp_num[main_bank_index];
assign core_rsp_req_rd = per_bank_wb_rd[main_bank_index];
assign core_rsp_req_wb = per_bank_wb_wb[main_bank_index];
assign core_rsp_warp_num = per_bank_wb_warp_num[main_bank_index];
integer this_bank;
generate
always @(*) begin
core_wb_valid = 0;
core_wb_readdata = 0;
core_wb_pc = 0;
core_wb_address = 0;
core_rsp_valid = 0;
core_rsp_readdata = 0;
core_rsp_pc = 0;
core_rsp_address = 0;
for (this_bank = 0; this_bank < NUM_BANKS; this_bank = this_bank + 1) begin
if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
if (found_bank
&& !core_wb_valid[per_bank_wb_tid[this_bank]]
&& !core_rsp_valid[per_bank_wb_tid[this_bank]]
&& per_bank_wb_valid[this_bank]
&& ((main_bank_index == `LOG2UP(NUM_BANKS)'(this_bank))
|| (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) begin
core_wb_valid[per_bank_wb_tid[this_bank]] = 1;
core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank];
core_wb_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank];
per_bank_wb_pop_unqual[this_bank] = 1;
core_rsp_valid[per_bank_wb_tid[this_bank]] = 1;
core_rsp_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_rsp_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank];
core_rsp_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank];
per_bank_wb_pop_unqual[this_bank] = 1;
end else begin
per_bank_wb_pop_unqual[this_bank] = 0;
per_bank_wb_pop_unqual[this_bank] = 0;
end
end else begin
if (((main_bank_index == `LOG2UP(NUM_BANKS)'(this_bank))
|| (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))
&& found_bank
&& !core_wb_valid[per_bank_wb_tid[this_bank]]
&& !core_rsp_valid[per_bank_wb_tid[this_bank]]
&& (per_bank_wb_valid[this_bank])
&& (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index])
&& (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin
core_wb_valid[per_bank_wb_tid[this_bank]] = 1;
core_wb_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_wb_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank];
core_wb_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank];
per_bank_wb_pop_unqual[this_bank] = 1;
core_rsp_valid[per_bank_wb_tid[this_bank]] = 1;
core_rsp_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_rsp_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank];
core_rsp_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank];
per_bank_wb_pop_unqual[this_bank] = 1;
end else begin
per_bank_wb_pop_unqual[this_bank] = 0;
per_bank_wb_pop_unqual[this_bank] = 0;
end
end
end

14
hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
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@@ -8,17 +8,17 @@ interface VX_gpu_dcache_rsp_if #(
) ();
// Core response
wire [NUM_REQUESTS-1:0] core_wb_valid;
wire [NUM_REQUESTS-1:0] core_rsp_valid;
`IGNORE_WARNINGS_BEGIN
wire [4:0] core_wb_req_rd;
wire [1:0] core_wb_req_wb;
wire [4:0] core_rsp_req_rd;
wire [1:0] core_rsp_req_wb;
`IGNORE_WARNINGS_END
wire [NUM_REQUESTS-1:0][31:0] core_wb_pc;
wire [NUM_REQUESTS-1:0][31:0] core_wb_readdata;
wire core_no_wb_slot;
wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc;
wire [NUM_REQUESTS-1:0][31:0] core_rsp_readdata;
wire core_rsp_ready;
// Core response meta data
wire [`NW_BITS-1:0] core_wb_warp_num;
wire [`NW_BITS-1:0] core_rsp_warp_num;
endinterface