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adding OPAE CSR support

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This commit is contained in:
Blaise Tine
2020-06-30 10:05:57 -07:00
parent 1f5c4bf617
commit 582a00d690
10 changed files with 334 additions and 94 deletions
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8
driver/rtlsim/Makefile
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@@ -21,7 +21,7 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2
#DEBUG=1
#AFU=1
AFU=1
CFLAGS += -fPIC
@@ -56,8 +56,10 @@ endif
# AFU
ifdef AFU
TOP = vortex_afu_sim
VL_FLAGS += -DNOPAE -DSCOPE
CFLAGS += -DNOPAE -DSCOPE
VL_FLAGS += -DNOPAE
CFLAGS += -DNOPAE
#VL_FLAGS += -DSCOPE
#CFLAGS += -DSCOPE
RTL_INCLUDE += -I../../hw/opae -I../../hw/opae/ccip
endif

51
hw/opae/vortex_afu.sv
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@@ -122,6 +122,17 @@ logic [`VX_SNP_TAG_WIDTH-1:0] vx_snp_rsp_tag;
`DEBUG_END
logic vx_snp_rsp_ready;
logic vx_csr_io_req_valid;
logic [`NC_BITS-1:0] vx_csr_io_req_coreid;
logic [11:0] vx_csr_io_req_addr;
logic vx_csr_io_req_rw;
logic [31:0] vx_csr_io_req_data;
logic vx_csr_io_req_ready;
logic vx_csr_io_rsp_valid;
logic [31:0] vx_csr_io_rsp_data;
logic vx_csr_io_rsp_ready;
logic vx_reset;
logic vx_busy;
@@ -156,7 +167,7 @@ logic cmd_scope_read;
logic cmd_scope_write;
`endif
logic [31:0] cmd_csr_addr;
logic [11:0] cmd_csr_addr;
logic [31:0] cmd_csr_rdata;
logic [31:0] cmd_csr_wdata;
@@ -278,7 +289,7 @@ begin
end
`endif
MMIO_CSR_READ: begin
mmio_tx.data <= cmd_csr_rdata;
mmio_tx.data <= 64'(cmd_csr_rdata);
`ifdef DBG_PRINT_OPAE
$display("%t: MMIO_CSR_READ: data=%0h", $time, cmd_csr_rdata);
`endif
@@ -854,20 +865,17 @@ end
// CSRs///////////////////////////////////////////////////////////////////////
assign cmd_csr_read_done = 1;
assign cmd_csr_write_done = 1;
assign vx_csr_io_req_valid = (STATE_CSR_READ == state || STATE_CSR_WRITE == state);
assign vx_csr_io_req_coreid = 0;
assign vx_csr_io_req_rw = (STATE_CSR_WRITE == state);
assign vx_csr_io_req_addr = cmd_csr_addr;
assign vx_csr_io_req_data = cmd_csr_wdata;
always_comb begin
case (cmd_csr_addr)
`CSR_VEND_ID : cmd_csr_rdata = `VENDOR_ID;
`CSR_ARCH_ID : cmd_csr_rdata = `ARCHITECTURE_ID;
`CSR_IMPL_ID : cmd_csr_rdata = `IMPLEMENTATION_ID;
`CSR_NT : cmd_csr_rdata = `NUM_THREADS;
`CSR_NW : cmd_csr_rdata = `NUM_WARPS;
`CSR_NC : cmd_csr_rdata = `NUM_CORES * `NUM_CLUSTERS;
default : cmd_csr_rdata = 0;
endcase
end
assign cmd_csr_rdata = vx_csr_io_rsp_data;
assign vx_csr_io_rsp_ready = 1;
assign cmd_csr_read_done = vx_csr_io_rsp_valid;
assign cmd_csr_write_done = vx_csr_io_req_ready;
// Vortex /////////////////////////////////////////////////////////////////////
@@ -926,6 +934,19 @@ Vortex #() vortex (
.io_rsp_tag (0),
`UNUSED_PIN (io_rsp_ready),
// CSR I/O Request
.csr_io_req_valid (vx_csr_io_req_valid),
.csr_io_req_coreid(vx_csr_io_req_coreid),
.csr_io_req_addr (vx_csr_io_req_addr),
.csr_io_req_rw (vx_csr_io_req_rw),
.csr_io_req_data (vx_csr_io_req_data),
.csr_io_req_ready (vx_csr_io_req_ready),
// CSR I/O Response
.csr_io_rsp_valid (vx_csr_io_rsp_valid),
.csr_io_rsp_data (vx_csr_io_rsp_data),
.csr_io_rsp_ready (vx_csr_io_rsp_ready),
// status
.busy (vx_busy),
`UNUSED_PIN (ebreak)

29
hw/opae/vortex_afu.vh
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@@ -12,17 +12,24 @@
`define AFU_ACCEL_NAME "vortex_afu"
`define AFU_ACCEL_UUID 128'h35f9452b_25c2_434c_93d5_6f8c60db361c
`define AFU_IMAGE_CMD_TYPE_CLFLUSH 4
`define AFU_IMAGE_CMD_TYPE_READ 1
`define AFU_IMAGE_CMD_TYPE_RUN 3
`define AFU_IMAGE_CMD_TYPE_WRITE 2
`define AFU_IMAGE_MMIO_CSR_CMD 10
`define AFU_IMAGE_MMIO_CSR_DATA_SIZE 12
`define AFU_IMAGE_MMIO_CSR_IO_ADDR 14
`define AFU_IMAGE_MMIO_CSR_MEM_ADDR 16
`define AFU_IMAGE_MMIO_CSR_STATUS 18
`define AFU_IMAGE_MMIO_CSR_SCOPE_CMD 20
`define AFU_IMAGE_MMIO_CSR_SCOPE_DATA 22
`define AFU_IMAGE_CMD_CLFLUSH 4
`define AFU_IMAGE_CMD_CSR_READ 5
`define AFU_IMAGE_CMD_CSR_WRITE 6
`define AFU_IMAGE_CMD_MEM_READ 1
`define AFU_IMAGE_CMD_MEM_WRITE 2
`define AFU_IMAGE_CMD_RUN 3
`define AFU_IMAGE_MMIO_CMD_TYPE 10
`define AFU_IMAGE_MMIO_CSR_ADDR 24
`define AFU_IMAGE_MMIO_CSR_DATA 26
`define AFU_IMAGE_MMIO_CSR_READ 28
`define AFU_IMAGE_MMIO_DATA_SIZE 16
`define AFU_IMAGE_MMIO_IO_ADDR 12
`define AFU_IMAGE_MMIO_MEM_ADDR 14
`define AFU_IMAGE_MMIO_SCOPE_READ 20
`define AFU_IMAGE_MMIO_SCOPE_WRITE 22
`define AFU_IMAGE_MMIO_STATUS 18
`define AFU_IMAGE_POWER 0
`define AFU_TOP_IFC "ccip_std_afu_avalon_mm"

3
hw/rtl/VX_back_end.v
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@@ -108,7 +108,7 @@ module VX_back_end #(
VX_wb_if csr_pipe_rsp();
VX_csr_arbiter csr_arbiter (
VX_csr_arb csr_arbiter (
.clk (clk),
.reset (reset),
.csr_pipe_stall(stall_gpr_csr),
@@ -119,7 +119,6 @@ module VX_back_end #(
.csr_pipe_rsp (csr_pipe_rsp),
.csr_wb_if (csr_wb_if),
.csr_io_rsp (io_csr_rsp)
);
VX_csr_pipe #(

77
hw/rtl/VX_cluster.v
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@@ -56,6 +56,19 @@ module VX_cluster #(
input wire [`L2CORE_TAG_WIDTH-1:0] io_rsp_tag,
output wire io_rsp_ready,
// CSR I/O Request
input wire csr_io_req_valid,
input wire [`NC_BITS-1:0] csr_io_req_coreid,
input wire [11:0] csr_io_req_addr,
input wire csr_io_req_rw,
input wire [31:0] csr_io_req_data,
output wire csr_io_req_ready,
// CSR I/O Response
output wire csr_io_rsp_valid,
output wire [31:0] csr_io_rsp_data,
input wire csr_io_rsp_ready,
// Status
output wire busy,
output wire ebreak
@@ -109,10 +122,22 @@ module VX_cluster #(
wire [`NUM_CORES-1:0][31:0] per_core_io_rsp_data;
wire [`NUM_CORES-1:0] per_core_io_rsp_ready;
wire [`NUM_CORES-1:0] per_core_csr_io_req_valid;
wire [`NUM_CORES-1:0][`NC_BITS-1:0] per_core_csr_io_req_coreid;
wire [`NUM_CORES-1:0][11:0] per_core_csr_io_req_addr;
wire [`NUM_CORES-1:0] per_core_csr_io_req_rw;
wire [`NUM_CORES-1:0][31:0] per_core_csr_io_req_data;
wire [`NUM_CORES-1:0] per_core_csr_io_req_ready;
wire [`NUM_CORES-1:0] per_core_csr_io_rsp_valid;
wire [`NUM_CORES-1:0][31:0] per_core_csr_io_rsp_data;
wire [`NUM_CORES-1:0] per_core_csr_io_rsp_ready;
wire [`NUM_CORES-1:0] per_core_busy;
wire [`NUM_CORES-1:0] per_core_ebreak;
genvar i;
for (i = 0; i < `NUM_CORES; i++) begin
VX_core #(
.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
@@ -174,18 +199,15 @@ module VX_cluster #(
.io_rsp_tag (per_core_io_rsp_tag [i]),
.io_rsp_ready (per_core_io_rsp_ready [i]),
.csr_io_req_valid (per_core_csr_io_req_valid[i] && (per_core_csr_io_req_coreid[i] == `NC_BITS'(i))),
.csr_io_req_rw (per_core_csr_io_req_rw [i]),
.csr_io_req_addr (per_core_csr_io_req_addr [i]),
.csr_io_req_data (per_core_csr_io_req_data [i]),
.csr_io_req_ready (per_core_csr_io_req_ready [i]),
.csr_io_req_valid (1'b0), // Valid CSR IO Request
`UNUSED_PIN(csr_io_req_ready), // Core is ready to accept Request
`UNUSED_PIN(csr_io_req_cid), // CORE_ID of the intended request
`UNUSED_PIN(csr_io_req_addr), // ADDRESS of request
`UNUSED_PIN(csr_io_req_rw), // Read=0, Write=1
`UNUSED_PIN(csr_io_req_data), // Data to write
`UNUSED_PIN(csr_io_rsp_valid), // Core IO Response valid
`UNUSED_PIN(csr_io_rsp_data), // Core IO Response data
.csr_io_rsp_valid (per_core_csr_io_rsp_valid [i]),
.csr_io_rsp_data (per_core_csr_io_rsp_data [i]),
.csr_io_rsp_ready (per_core_csr_io_rsp_ready [i]),
.busy (per_core_busy [i]),
.ebreak (per_core_ebreak [i])
@@ -232,6 +254,39 @@ module VX_cluster #(
.out_mem_rsp_ready (io_rsp_ready)
);
VX_csr_io_arb #(
.NUM_REQUESTS (`NUM_CORES)
) csr_io_arb (
.clk (clk),
.reset (reset),
// input requests
.in_csr_io_req_valid (csr_io_req_valid),
.in_csr_io_req_coreid (csr_io_req_coreid),
.in_csr_io_req_addr (csr_io_req_addr),
.in_csr_io_req_rw (csr_io_req_rw),
.in_csr_io_req_data (csr_io_req_data),
.in_csr_io_req_ready (csr_io_req_ready),
// input responses
.in_csr_io_rsp_valid (per_core_csr_io_rsp_valid),
.in_csr_io_rsp_data (per_core_csr_io_rsp_data),
.in_csr_io_rsp_ready (per_core_csr_io_rsp_ready),
// output request
.out_csr_io_req_valid (per_core_csr_io_req_valid),
.out_csr_io_req_coreid (per_core_csr_io_req_coreid),
.out_csr_io_req_addr (per_core_csr_io_req_addr),
.out_csr_io_req_rw (per_core_csr_io_req_rw),
.out_csr_io_req_data (per_core_csr_io_req_data),
.out_csr_io_req_ready (per_core_csr_io_req_ready),
// output response
.out_csr_io_rsp_valid (csr_io_rsp_valid),
.out_csr_io_rsp_data (csr_io_rsp_data),
.out_csr_io_rsp_ready (csr_io_rsp_ready)
);
assign busy = (| per_core_busy);
assign ebreak = (& per_core_ebreak);

16
hw/rtl/VX_core.v
View File

@@ -70,46 +70,45 @@ module VX_core #(
input wire [`DCORE_TAG_WIDTH-1:0] io_rsp_tag,
output wire io_rsp_ready,
// IO CSR Request
// CSR I/O Request
input wire csr_io_req_valid,
input wire[`NC_BITS-1:0] csr_io_req_cid,
input wire[11:0] csr_io_req_addr,
input wire csr_io_req_rw,
input wire[31:0] csr_io_req_data,
output wire csr_io_req_ready,
// IO CSR Response
// CSR I/O Response
output wire csr_io_rsp_valid,
output wire[31:0] csr_io_rsp_data,
input wire csr_io_rsp_ready,
// Status
output wire busy,
output wire ebreak
);
`UNUSED_VAR(csr_io_rsp_ready)
// IO CSR request
VX_csr_req_if io_csr_req();
wire temp_io_csr_req_valid = csr_io_req_valid & (csr_io_req_cid == CORE_ID[`NC_BITS-1:0]);
wire temp_io_csr_req_valid = csr_io_req_valid;
assign io_csr_req.valid = {`NUM_THREADS{temp_io_csr_req_valid}};
assign io_csr_req.is_csr = 1'b1;
assign io_csr_req.csr_address = csr_io_req_addr;
assign io_csr_req.alu_op = csr_io_req_rw ? `ALU_CSR_RW : `ALU_CSR_RS;
assign io_csr_req.csr_mask = csr_io_req_rw ? csr_io_req_data : 32'b0;
VX_wb_if io_csr_rsp();
assign csr_io_req_ready = io_csr_rsp.is_io;
assign csr_io_rsp_valid = io_csr_rsp.valid[0];
assign csr_io_rsp_data = io_csr_rsp.data[0];
`IGNORE_WARNINGS_BEGIN
wire [4:0] unused_rd = io_csr_rsp.rd;
wire [1:0] unused_wb = io_csr_rsp.wb;
wire [31:0] unused_curr_PC = io_csr_rsp.curr_PC;
`IGNORE_WARNINGS_END
// Dcache Interfaces
VX_cache_dram_req_if #(
.DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH),
@@ -213,7 +212,6 @@ module VX_core #(
.clk(clk),
.reset(reset),
// IO CSR
.io_csr_req (io_csr_req),
.io_csr_rsp (io_csr_rsp),

10
hw/rtl/VX_csr_arbiter.v → hw/rtl/VX_csr_arb.v
View File

@@ -1,25 +1,23 @@
`include "VX_define.vh"
module VX_csr_arbiter (
module VX_csr_arb (
input wire clk,
input wire reset,
input wire csr_pipe_stall,
VX_csr_req_if core_csr_req,
VX_csr_req_if io_csr_req,
VX_csr_req_if issued_csr_req,
VX_wb_if csr_pipe_rsp,
VX_wb_if csr_wb_if,
VX_wb_if csr_io_rsp
);
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
wire pick_core = (|core_csr_req.valid);
// Which request to pick
@@ -37,8 +35,6 @@ module VX_csr_arbiter (
assign issued_csr_req.rd = core_csr_req.rd;
assign issued_csr_req.wb = core_csr_req.wb;
// Core Writeback
assign csr_wb_if.valid = csr_pipe_rsp.valid & {`NUM_THREADS{~csr_pipe_rsp.is_io}};
@@ -59,6 +55,4 @@ module VX_csr_arbiter (
assign csr_io_rsp.curr_PC = csr_pipe_rsp.curr_PC;
assign csr_io_rsp.is_io = !(csr_pipe_stall || pick_core);
endmodule

85
hw/rtl/VX_csr_io_arb.v Normal file
View File

@@ -0,0 +1,85 @@
`include "VX_define.vh"
module VX_csr_io_arb #(
parameter NUM_REQUESTS = 1,
parameter REQS_BITS = `CLOG2(NUM_REQUESTS)
) (
input wire clk,
input wire reset,
// input requests
input wire in_csr_io_req_valid,
input wire [`NC_BITS-1:0] in_csr_io_req_coreid,
input wire [11:0] in_csr_io_req_addr,
input wire in_csr_io_req_rw,
input wire [31:0] in_csr_io_req_data,
output wire in_csr_io_req_ready,
// input response
input wire [NUM_REQUESTS-1:0] in_csr_io_rsp_valid,
input wire [NUM_REQUESTS-1:0][31:0] in_csr_io_rsp_data,
output wire [NUM_REQUESTS-1:0] in_csr_io_rsp_ready,
// output request
output wire [NUM_REQUESTS-1:0] out_csr_io_req_valid,
output wire [NUM_REQUESTS-1:0][`NC_BITS-1:0] out_csr_io_req_coreid,
output wire [NUM_REQUESTS-1:0][11:0] out_csr_io_req_addr,
output wire [NUM_REQUESTS-1:0] out_csr_io_req_rw,
output wire [NUM_REQUESTS-1:0][31:0] out_csr_io_req_data,
input wire [NUM_REQUESTS-1:0] out_csr_io_req_ready,
// output response
output wire out_csr_io_rsp_valid,
output wire [31:0] out_csr_io_rsp_data,
input wire out_csr_io_rsp_ready
);
if (NUM_REQUESTS == 1) begin
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
assign out_csr_io_req_valid = in_csr_io_req_valid;
assign out_csr_io_req_coreid = in_csr_io_req_coreid;
assign out_csr_io_req_rw = in_csr_io_req_rw;
assign out_csr_io_req_addr = in_csr_io_req_addr;
assign out_csr_io_req_data = in_csr_io_req_data;
assign in_csr_io_req_ready = out_csr_io_req_ready;
assign out_csr_io_rsp_valid = in_csr_io_rsp_valid;
assign out_csr_io_rsp_data = in_csr_io_rsp_data;
assign in_csr_io_rsp_ready = out_csr_io_rsp_ready;
end else begin
reg [REQS_BITS-1:0] bus_rsp_sel;
VX_fixed_arbiter #(
.N(NUM_REQUESTS)
) arbiter (
.clk (clk),
.reset (reset),
.requests (in_csr_io_rsp_valid),
.grant_index (bus_rsp_sel),
`UNUSED_PIN (grant_valid),
`UNUSED_PIN (grant_onehot)
);
assign out_csr_io_rsp_valid = in_csr_io_rsp_valid [bus_rsp_sel];
assign out_csr_io_rsp_data = in_csr_io_rsp_data [bus_rsp_sel];
assign in_csr_io_rsp_ready [bus_rsp_sel] = out_csr_io_rsp_ready;
genvar i;
for (i = 0; i < NUM_REQUESTS; i++) begin
assign out_csr_io_req_valid[i] = in_csr_io_req_valid && in_csr_io_req_ready;
assign out_csr_io_req_coreid[i] = in_csr_io_req_coreid;
assign out_csr_io_req_rw[i] = in_csr_io_req_rw;
assign out_csr_io_req_addr[i] = in_csr_io_req_addr;
assign out_csr_io_req_data[i] = in_csr_io_req_data;
end
assign in_csr_io_req_ready = (& out_csr_io_req_ready);
end
endmodule

79
hw/rtl/Vortex.v
View File

@@ -54,6 +54,19 @@ module Vortex (
input wire [`VX_CORE_TAG_WIDTH-1:0] io_rsp_tag,
output wire io_rsp_ready,
// CSR I/O Request
input wire csr_io_req_valid,
input wire [`NC_BITS-1:0] csr_io_req_coreid,
input wire [11:0] csr_io_req_addr,
input wire csr_io_req_rw,
input wire [31:0] csr_io_req_data,
output wire csr_io_req_ready,
// CSR I/O Response
output wire csr_io_rsp_valid,
output wire [31:0] csr_io_rsp_data,
input wire csr_io_rsp_ready,
// Status
output wire busy,
output wire ebreak
@@ -109,6 +122,17 @@ module Vortex (
.io_rsp_tag (io_rsp_tag),
.io_rsp_ready (io_rsp_ready),
.csr_io_req_valid (csr_io_req_valid),
.csr_io_req_coreid (csr_io_req_coreid),
.csr_io_req_rw (csr_io_req_rw),
.csr_io_req_addr (csr_io_req_addr),
.csr_io_req_data (csr_io_req_data),
.csr_io_req_ready (csr_io_req_ready),
.csr_io_rsp_valid (csr_io_rsp_valid),
.csr_io_rsp_data (csr_io_rsp_data),
.csr_io_rsp_ready (csr_io_rsp_ready),
.busy (busy),
.ebreak (ebreak)
);
@@ -151,6 +175,17 @@ module Vortex (
wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_rsp_data;
wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_valid;
wire [`NUM_CLUSTERS-1:0][`NC_BITS-1:0] per_cluster_csr_io_req_coreid;
wire [`NUM_CLUSTERS-1:0][11:0] per_cluster_csr_io_req_addr;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_rw;
wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_req_data;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_valid;
wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_rsp_data;
wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_ready;
wire [`NUM_CLUSTERS-1:0] per_cluster_busy;
wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak;
@@ -205,6 +240,17 @@ module Vortex (
.io_rsp_tag (per_cluster_io_rsp_tag [i]),
.io_rsp_ready (per_cluster_io_rsp_ready [i]),
.csr_io_req_valid (per_cluster_csr_io_req_valid[i]),
.csr_io_req_coreid (per_cluster_csr_io_req_coreid[i]),
.csr_io_req_rw (per_cluster_csr_io_req_rw [i]),
.csr_io_req_addr (per_cluster_csr_io_req_addr[i]),
.csr_io_req_data (per_cluster_csr_io_req_data[i]),
.csr_io_req_ready (per_cluster_csr_io_req_ready[i]),
.csr_io_rsp_valid (per_cluster_csr_io_rsp_valid[i]),
.csr_io_rsp_data (per_cluster_csr_io_rsp_data[i]),
.csr_io_rsp_ready (per_cluster_csr_io_rsp_ready[i]),
.busy (per_cluster_busy [i]),
.ebreak (per_cluster_ebreak [i])
);
@@ -250,6 +296,39 @@ module Vortex (
.out_mem_rsp_ready (io_rsp_ready)
);
VX_csr_io_arb #(
.NUM_REQUESTS (`NUM_CLUSTERS)
) csr_io_arb (
.clk (clk),
.reset (reset),
// input requests
.in_csr_io_req_valid (csr_io_req_valid),
.in_csr_io_req_coreid (csr_io_req_coreid),
.in_csr_io_req_addr (csr_io_req_addr),
.in_csr_io_req_rw (csr_io_req_rw),
.in_csr_io_req_data (csr_io_req_data),
.in_csr_io_req_ready (csr_io_req_ready),
// input responses
.in_csr_io_rsp_valid (per_cluster_csr_io_rsp_valid),
.in_csr_io_rsp_data (per_cluster_csr_io_rsp_data),
.in_csr_io_rsp_ready (per_cluster_csr_io_rsp_ready),
// output request
.out_csr_io_req_valid (per_cluster_csr_io_req_valid),
.out_csr_io_req_coreid (per_cluster_csr_io_req_coreid),
.out_csr_io_req_addr (per_cluster_csr_io_req_addr),
.out_csr_io_req_rw (per_cluster_csr_io_req_rw),
.out_csr_io_req_data (per_cluster_csr_io_req_data),
.out_csr_io_req_ready (per_cluster_csr_io_req_ready),
// output response
.out_csr_io_rsp_valid (csr_io_rsp_valid),
.out_csr_io_rsp_data (csr_io_rsp_data),
.out_csr_io_rsp_ready (csr_io_rsp_ready)
);
assign busy = (| per_cluster_busy);
assign ebreak = (& per_cluster_ebreak);

2
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -88,7 +88,7 @@ module VX_snp_forwarder #(
genvar i;
for (i = 0; i < NUM_REQUESTS; i++) begin
assign snp_fwdout_valid[i] = snp_req_valid && !sfq_full;
assign snp_fwdout_valid[i] = snp_req_valid && snp_req_ready;
assign snp_fwdout_addr[i] = snp_req_addr;
assign snp_fwdout_invalidate[i] = snp_req_invalidate;
assign snp_fwdout_tag[i] = sfq_write_addr;