59 lines
2.1 KiB
Verilog
59 lines
2.1 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_arb (
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input wire clk,
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input wire reset,
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input wire csr_pipe_stall,
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VX_csr_req_if core_csr_req,
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VX_csr_req_if io_csr_req,
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VX_csr_req_if issued_csr_req,
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VX_wb_if csr_pipe_rsp,
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VX_wb_if csr_wb_if,
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VX_wb_if csr_io_rsp
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);
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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wire pick_core = (|core_csr_req.valid);
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// Which request to pick
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assign issued_csr_req.is_io = !pick_core;
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// Mux between core and io
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assign issued_csr_req.valid = pick_core ? core_csr_req.valid : io_csr_req.valid;
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assign issued_csr_req.is_csr = pick_core ? core_csr_req.is_csr : io_csr_req.is_csr;
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assign issued_csr_req.alu_op = pick_core ? core_csr_req.alu_op : io_csr_req.alu_op;
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assign issued_csr_req.csr_address = pick_core ? core_csr_req.csr_address : io_csr_req.csr_address;
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assign issued_csr_req.csr_mask = pick_core ? core_csr_req.csr_mask : io_csr_req.csr_mask;
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// Core arguments
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assign issued_csr_req.warp_num = core_csr_req.warp_num;
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assign issued_csr_req.rd = core_csr_req.rd;
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assign issued_csr_req.wb = core_csr_req.wb;
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// Core Writeback
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assign csr_wb_if.valid = csr_pipe_rsp.valid & {`NUM_THREADS{~csr_pipe_rsp.is_io}};
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assign csr_wb_if.data = csr_pipe_rsp.data;
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assign csr_wb_if.warp_num = csr_pipe_rsp.warp_num;
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assign csr_wb_if.rd = csr_pipe_rsp.rd;
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assign csr_wb_if.wb = csr_pipe_rsp.wb;
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assign csr_wb_if.curr_PC = csr_pipe_rsp.curr_PC;
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assign csr_wb_if.is_io = 1'b0;
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// CSR IO WB
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assign csr_io_rsp.valid = csr_pipe_rsp.valid & {`NUM_THREADS{csr_pipe_rsp.is_io}};
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assign csr_io_rsp.data = csr_pipe_rsp.data;
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assign csr_io_rsp.warp_num = csr_pipe_rsp.warp_num;
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assign csr_io_rsp.rd = csr_pipe_rsp.rd;
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assign csr_io_rsp.wb = csr_pipe_rsp.wb;
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assign csr_io_rsp.curr_PC = csr_pipe_rsp.curr_PC;
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assign csr_io_rsp.is_io = !(csr_pipe_stall || pick_core);
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endmodule
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