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OPAE rtl fixes

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This commit is contained in:
Blaise Tine
2020-06-04 15:44:03 -07:00
parent ea890b457d
commit 4e0e710182
8 changed files with 49 additions and 68 deletions
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6
hw/rtl/VX_config.vh
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@@ -224,7 +224,7 @@
// Number of banks {1, 2, 4, 8,...}
`ifndef SNUM_BANKS
`define SNUM_BANKS 8
`define SNUM_BANKS 4
`endif
// Size of a word in bytes
@@ -261,7 +261,7 @@
// Number of banks {1, 2, 4, 8,...}
`ifndef L2NUM_BANKS
`define L2NUM_BANKS 8
`define L2NUM_BANKS 4
`endif
// Size of a word in bytes
@@ -332,7 +332,7 @@
// Number of banks {1, 2, 4, 8,...}
`ifndef L3NUM_BANKS
`define L3NUM_BANKS 8
`define L3NUM_BANKS 4
`endif
// Size of a word in bytes

8
hw/rtl/VX_define.vh
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@@ -57,11 +57,13 @@
///////////////////////////////////////////////////////////////////////////////
`define NW_BITS (`LOG2UP(`NUM_WARPS))
`define NW_BITS `LOG2UP(`NUM_WARPS)
`define NT_BITS (`LOG2UP(`NUM_THREADS))
`define NT_BITS `LOG2UP(`NUM_THREADS)
`define NC_BITS (`LOG2UP(`NUM_CORES))
`define NC_BITS `LOG2UP(`NUM_CORES)
`define REQS_BITS `LOG2UP(NUM_REQUESTS)
`define NUM_GPRS 32

25
hw/rtl/VX_dram_arb.v
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@@ -1,10 +1,13 @@
`include "VX_define.vh"
module VX_dram_arb #(
parameter BANK_LINE_SIZE = 1,
module VX_dram_arb #(
parameter NUM_REQUESTS = 1,
parameter DRAM_LINE_SIZE = 1,
parameter CORE_TAG_WIDTH = 1,
parameter DRAM_TAG_WIDTH = 1
parameter DRAM_TAG_WIDTH = 1,
parameter DRAM_LINE_WIDTH = DRAM_LINE_SIZE * 8,
parameter DRAM_ADDR_WIDTH = 32 - `CLOG2(DRAM_LINE_SIZE)
) (
input wire clk,
input wire reset,
@@ -12,30 +15,30 @@ module VX_dram_arb #(
// Core request
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0] core_req_rw,
input wire [NUM_REQUESTS-1:0][BANK_LINE_SIZE-1:0] core_req_byteen,
input wire [NUM_REQUESTS-1:0][`DRAM_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`BANK_LINE_WIDTH-1:0] core_req_data,
input wire [NUM_REQUESTS-1:0][DRAM_LINE_SIZE-1:0] core_req_byteen,
input wire [NUM_REQUESTS-1:0][DRAM_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][DRAM_LINE_WIDTH-1:0] core_req_data,
input wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire [NUM_REQUESTS-1:0] core_req_ready,
// Core response
output wire [NUM_REQUESTS-1:0] core_rsp_valid,
output wire [NUM_REQUESTS-1:0][`BANK_LINE_WIDTH-1:0]core_rsp_data,
output wire [NUM_REQUESTS-1:0][DRAM_LINE_WIDTH-1:0] core_rsp_data,
output wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire [NUM_REQUESTS-1:0] core_rsp_ready,
// DRAM request
output wire dram_req_valid,
output wire dram_req_rw,
output wire [BANK_LINE_SIZE-1:0] dram_req_byteen,
output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [`BANK_LINE_WIDTH-1:0] dram_req_data,
output wire [DRAM_LINE_SIZE-1:0] dram_req_byteen,
output wire [DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [DRAM_LINE_WIDTH-1:0] dram_req_data,
output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag,
input wire dram_req_ready,
// DRAM response
input wire dram_rsp_valid,
input wire [`BANK_LINE_WIDTH-1:0] dram_rsp_data,
input wire [DRAM_LINE_WIDTH-1:0] dram_rsp_data,
input wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready
);

2
hw/rtl/Vortex_Cluster.v
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@@ -423,8 +423,8 @@ module Vortex_Cluster #(
);
VX_dram_arb #(
.BANK_LINE_SIZE (`L2BANK_LINE_SIZE),
.NUM_REQUESTS (`L2NUM_REQUESTS),
.DRAM_LINE_SIZE (`L2BANK_LINE_SIZE),
.CORE_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH)
) dram_arb (

2
hw/rtl/cache/VX_cache_config.vh vendored
View File

@@ -11,8 +11,6 @@
// data metadata word_sel is_snp
`define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_WIDTH) + 1)
`define REQS_BITS `LOG2UP(NUM_REQUESTS)
`define BANK_BITS `LOG2UP(NUM_BANKS)
`define WORD_WIDTH (8 * WORD_SIZE)