From 4e0e710182521c99160b2dcee3ab2d56ca7a376f Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 4 Jun 2020 15:44:03 -0700 Subject: [PATCH] OPAE rtl fixes --- hw/opae/Makefile | 55 +++++++++++++++------------------ hw/opae/README | 2 +- hw/opae/sources.txt | 17 ---------- hw/rtl/VX_config.vh | 6 ++-- hw/rtl/VX_define.vh | 8 +++-- hw/rtl/VX_dram_arb.v | 25 ++++++++------- hw/rtl/Vortex_Cluster.v | 2 +- hw/rtl/cache/VX_cache_config.vh | 2 -- 8 files changed, 49 insertions(+), 68 deletions(-) diff --git a/hw/opae/Makefile b/hw/opae/Makefile index a3402664..039f01d2 100644 --- a/hw/opae/Makefile +++ b/hw/opae/Makefile @@ -1,61 +1,56 @@ - ASE_BUILD_DIR=build_ase + FPGA_BUILD_DIR=build_fpga -all: ase - -ase: setup-ase - make -C $(ASE_BUILD_DIR) - -setup-ase: $(ASE_BUILD_DIR)/Makefile - -$(ASE_BUILD_DIR)/Makefile: - afu_sim_setup -s sources.txt $(ASE_BUILD_DIR) +all: ase-2c ase-1c: setup-ase-1c make -C $(ASE_BUILD_DIR)_1c +ase-2c: setup-ase-2c + make -C $(ASE_BUILD_DIR)_2c + setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile +setup-ase-2c: $(ASE_BUILD_DIR)_2c/Makefile + $(ASE_BUILD_DIR)_1c/Makefile: afu_sim_setup -s sources_1c.txt $(ASE_BUILD_DIR)_1c -fpga: setup-fpga - cd $(FPGA_BUILD_DIR) && qsub-synth - -setup-fpga: $(FPGA_BUILD_DIR)/build/dcp.qpf - -$(FPGA_BUILD_DIR)/build/dcp.qpf: - afu_synth_setup -s sources.txt $(FPGA_BUILD_DIR) +$(ASE_BUILD_DIR)_2c/Makefile: + afu_sim_setup -s sources_2c.txt $(ASE_BUILD_DIR)_2c fpga-1c: setup-fpga-1c cd $(FPGA_BUILD_DIR)_1c && qsub-synth + +fpga-2c: setup-fpga-2c + cd $(FPGA_BUILD_DIR)_2c && qsub-synth setup-fpga-1c: $(FPGA_BUILD_DIR)_1c/build/dcp.qpf +setup-fpga-2c: $(FPGA_BUILD_DIR)_2c/build/dcp.qpf + $(FPGA_BUILD_DIR)_1c/build/dcp.qpf: afu_synth_setup -s sources_1c.txt $(FPGA_BUILD_DIR)_1c -run-ase: - cd $(ASE_BUILD_DIR) && make sim +$(FPGA_BUILD_DIR)_2c/build/dcp.qpf: + afu_synth_setup -s sources_2c.txt $(FPGA_BUILD_DIR)_2c run-ase-1c: cd $(ASE_BUILD_DIR)_1c && make sim -wave: - vsim -view $(ASE_BUILD_DIR)/work/vsim.wlf -do wave.do - -run-fpga: - # TODO - -clean-ase: - rm -rf $(ASE_BUILD_DIR) +run-ase-2c: + cd $(ASE_BUILD_DIR)_2c && make sim clean-ase-1c: rm -rf $(ASE_BUILD_DIR)_1c -clean-fpga: - rm -rf $(FPGA_BUILD_DIR) +clean-ase-2c: + rm -rf $(ASE_BUILD_DIR)_2c clean-fpga-1c: - rm -rf $(FPGA_BUILD_DIR)_1c \ No newline at end of file + rm -rf $(FPGA_BUILD_DIR)_1c + +clean-fpga-2c: + rm -rf $(FPGA_BUILD_DIR)_2c + diff --git a/hw/opae/README b/hw/opae/README index d5aadd97..ffcf562b 100644 --- a/hw/opae/README +++ b/hw/opae/README @@ -82,4 +82,4 @@ ps -u tinebp kill -9 # fixing device resource busy issue when deleting /build_ase/ -- \ No newline at end of file +lsof +D build_ase \ No newline at end of file diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index 664af3ca..ff10bf62 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -1,22 +1,5 @@ vortex_afu.json -+define+DCACHE_SIZE=4096 -+define+ICACHE_SIZE=2048 -+define+SCACHE_SIZE=1024 - -+define+NUM_CORES=2 -+define+NUM_WARPS=4 -+define+NUM_THREADS=4 -+define+L2_ENABLE=1 - -+define+DNUM_BANKS=4 -+define+INUM_BANKS=1 -+define+SNUM_BANKS=4 - -+define+DDFPQ_SIZE=16 -+define+IDFPQ_SIZE=16 -+define+SDFPQ_SIZE=0 - #+define+DBG_PRINT_CORE_ICACHE #+define+DBG_PRINT_CORE_DCACHE #+define+DBG_PRINT_CACHE_BANK diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 1c3628e7..2eb2ff5e 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -224,7 +224,7 @@ // Number of banks {1, 2, 4, 8,...} `ifndef SNUM_BANKS -`define SNUM_BANKS 8 +`define SNUM_BANKS 4 `endif // Size of a word in bytes @@ -261,7 +261,7 @@ // Number of banks {1, 2, 4, 8,...} `ifndef L2NUM_BANKS -`define L2NUM_BANKS 8 +`define L2NUM_BANKS 4 `endif // Size of a word in bytes @@ -332,7 +332,7 @@ // Number of banks {1, 2, 4, 8,...} `ifndef L3NUM_BANKS -`define L3NUM_BANKS 8 +`define L3NUM_BANKS 4 `endif // Size of a word in bytes diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 45033d57..76dbd681 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -57,11 +57,13 @@ /////////////////////////////////////////////////////////////////////////////// -`define NW_BITS (`LOG2UP(`NUM_WARPS)) +`define NW_BITS `LOG2UP(`NUM_WARPS) -`define NT_BITS (`LOG2UP(`NUM_THREADS)) +`define NT_BITS `LOG2UP(`NUM_THREADS) -`define NC_BITS (`LOG2UP(`NUM_CORES)) +`define NC_BITS `LOG2UP(`NUM_CORES) + +`define REQS_BITS `LOG2UP(NUM_REQUESTS) `define NUM_GPRS 32 diff --git a/hw/rtl/VX_dram_arb.v b/hw/rtl/VX_dram_arb.v index 6d91a959..1140b01d 100644 --- a/hw/rtl/VX_dram_arb.v +++ b/hw/rtl/VX_dram_arb.v @@ -1,10 +1,13 @@ `include "VX_define.vh" -module VX_dram_arb #( - parameter BANK_LINE_SIZE = 1, +module VX_dram_arb #( parameter NUM_REQUESTS = 1, + parameter DRAM_LINE_SIZE = 1, parameter CORE_TAG_WIDTH = 1, - parameter DRAM_TAG_WIDTH = 1 + parameter DRAM_TAG_WIDTH = 1, + + parameter DRAM_LINE_WIDTH = DRAM_LINE_SIZE * 8, + parameter DRAM_ADDR_WIDTH = 32 - `CLOG2(DRAM_LINE_SIZE) ) ( input wire clk, input wire reset, @@ -12,30 +15,30 @@ module VX_dram_arb #( // Core request input wire [NUM_REQUESTS-1:0] core_req_valid, input wire [NUM_REQUESTS-1:0] core_req_rw, - input wire [NUM_REQUESTS-1:0][BANK_LINE_SIZE-1:0] core_req_byteen, - input wire [NUM_REQUESTS-1:0][`DRAM_ADDR_WIDTH-1:0] core_req_addr, - input wire [NUM_REQUESTS-1:0][`BANK_LINE_WIDTH-1:0] core_req_data, + input wire [NUM_REQUESTS-1:0][DRAM_LINE_SIZE-1:0] core_req_byteen, + input wire [NUM_REQUESTS-1:0][DRAM_ADDR_WIDTH-1:0] core_req_addr, + input wire [NUM_REQUESTS-1:0][DRAM_LINE_WIDTH-1:0] core_req_data, input wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag, output wire [NUM_REQUESTS-1:0] core_req_ready, // Core response output wire [NUM_REQUESTS-1:0] core_rsp_valid, - output wire [NUM_REQUESTS-1:0][`BANK_LINE_WIDTH-1:0]core_rsp_data, + output wire [NUM_REQUESTS-1:0][DRAM_LINE_WIDTH-1:0] core_rsp_data, output wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag, input wire [NUM_REQUESTS-1:0] core_rsp_ready, // DRAM request output wire dram_req_valid, output wire dram_req_rw, - output wire [BANK_LINE_SIZE-1:0] dram_req_byteen, - output wire [`DRAM_ADDR_WIDTH-1:0] dram_req_addr, - output wire [`BANK_LINE_WIDTH-1:0] dram_req_data, + output wire [DRAM_LINE_SIZE-1:0] dram_req_byteen, + output wire [DRAM_ADDR_WIDTH-1:0] dram_req_addr, + output wire [DRAM_LINE_WIDTH-1:0] dram_req_data, output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag, input wire dram_req_ready, // DRAM response input wire dram_rsp_valid, - input wire [`BANK_LINE_WIDTH-1:0] dram_rsp_data, + input wire [DRAM_LINE_WIDTH-1:0] dram_rsp_data, input wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag, output wire dram_rsp_ready ); diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index cafb47a1..aa7e981d 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -423,8 +423,8 @@ module Vortex_Cluster #( ); VX_dram_arb #( - .BANK_LINE_SIZE (`L2BANK_LINE_SIZE), .NUM_REQUESTS (`L2NUM_REQUESTS), + .DRAM_LINE_SIZE (`L2BANK_LINE_SIZE), .CORE_TAG_WIDTH (`DDRAM_TAG_WIDTH), .DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH) ) dram_arb ( diff --git a/hw/rtl/cache/VX_cache_config.vh b/hw/rtl/cache/VX_cache_config.vh index 7d163a73..71452e96 100644 --- a/hw/rtl/cache/VX_cache_config.vh +++ b/hw/rtl/cache/VX_cache_config.vh @@ -11,8 +11,6 @@ // data metadata word_sel is_snp `define MRVQ_METADATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_WIDTH) + 1) -`define REQS_BITS `LOG2UP(NUM_REQUESTS) - `define BANK_BITS `LOG2UP(NUM_BANKS) `define WORD_WIDTH (8 * WORD_SIZE)