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scope fixes

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This commit is contained in:
Blaise Tine
2020-10-13 08:44:55 -07:00
parent 99e209b7a2
commit 4bfc4ee78f
13 changed files with 56 additions and 42 deletions
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2
hw/rtl/VX_cluster.v
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@@ -372,7 +372,7 @@ module VX_cluster #(
.SNP_REQ_TAG_WIDTH (`L2SNP_TAG_WIDTH),
.SNP_FWD_TAG_WIDTH (`DSNP_TAG_WIDTH)
) l2cache (
`SCOPE_BIND_VX_cluster_l2cache()
`SCOPE_BIND_VX_cluster_l2cache
.clk (clk),
.reset (reset),

4
hw/rtl/VX_core.v
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@@ -175,7 +175,7 @@ module VX_core #(
VX_pipeline #(
.CORE_ID(CORE_ID)
) pipeline (
`SCOPE_BIND_VX_core_pipeline()
`SCOPE_BIND_VX_core_pipeline
.clk(clk),
.reset(reset),
@@ -251,7 +251,7 @@ module VX_core #(
VX_mem_unit #(
.CORE_ID(CORE_ID)
) mem_unit (
`SCOPE_BIND_VX_core_mem_unit()
`SCOPE_BIND_VX_core_mem_unit
.clk (clk),
.reset (reset),

4
hw/rtl/VX_execute.v
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@@ -54,7 +54,7 @@ module VX_execute #(
VX_lsu_unit #(
.CORE_ID(CORE_ID)
) lsu_unit (
`SCOPE_BIND_VX_execute_lsu_unit()
`SCOPE_BIND_VX_execute_lsu_unit
.clk (clk),
.reset (reset),
.dcache_req_if (dcache_req_if),
@@ -121,7 +121,7 @@ module VX_execute #(
VX_gpu_unit #(
.CORE_ID(CORE_ID)
) gpu_unit (
`SCOPE_BIND_VX_execute_gpu_unit()
`SCOPE_BIND_VX_execute_gpu_unit
.clk (clk),
.reset (reset),
.gpu_req_if (gpu_req_if),

4
hw/rtl/VX_fetch.v
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@@ -29,7 +29,7 @@ module VX_fetch #(
VX_warp_sched #(
.CORE_ID(CORE_ID)
) warp_sched (
`SCOPE_BIND_VX_fetch_warp_sched()
`SCOPE_BIND_VX_fetch_warp_sched
.clk (clk),
.reset (reset),
@@ -45,7 +45,7 @@ module VX_fetch #(
VX_icache_stage #(
.CORE_ID(CORE_ID)
) icache_stage (
`SCOPE_BIND_VX_fetch_icache_stage()
`SCOPE_BIND_VX_fetch_icache_stage
.clk (clk),
.reset (reset),

6
hw/rtl/VX_mem_unit.v
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@@ -77,7 +77,7 @@ module VX_mem_unit # (
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
) smem (
`SCOPE_BIND_VX_mem_unit_smem()
`SCOPE_BIND_VX_mem_unit_smem
.clk (clk),
.reset (reset),
@@ -159,7 +159,7 @@ module VX_mem_unit # (
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.SNP_REQ_TAG_WIDTH (`DSNP_TAG_WIDTH)
) dcache (
`SCOPE_BIND_VX_mem_unit_dcache()
`SCOPE_BIND_VX_mem_unit_dcache
.clk (clk),
.reset (reset),
@@ -240,7 +240,7 @@ module VX_mem_unit # (
.CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)
) icache (
`SCOPE_BIND_VX_mem_unit_icache()
`SCOPE_BIND_VX_mem_unit_icache
.clk (clk),
.reset (reset),

6
hw/rtl/VX_pipeline.v
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@@ -123,7 +123,7 @@ module VX_pipeline #(
VX_fetch #(
.CORE_ID(CORE_ID)
) fetch (
`SCOPE_BIND_VX_pipeline_fetch()
`SCOPE_BIND_VX_pipeline_fetch
.clk (clk),
.reset (reset),
.icache_req_if (core_icache_req_if),
@@ -150,7 +150,7 @@ module VX_pipeline #(
VX_issue #(
.CORE_ID(CORE_ID)
) issue (
`SCOPE_BIND_VX_pipeline_issue()
`SCOPE_BIND_VX_pipeline_issue
.clk (clk),
.reset (reset),
@@ -170,7 +170,7 @@ module VX_pipeline #(
VX_execute #(
.CORE_ID(CORE_ID)
) execute (
`SCOPE_BIND_VX_pipeline_execute()
`SCOPE_BIND_VX_pipeline_execute
.clk (clk),
.reset (reset),

34
hw/rtl/VX_scope.vh
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@@ -15,15 +15,19 @@
`define SCOPE_IO_VX_fetch
`define SCOPE_BIND_VX_fetch_icache_stage()
`define SCOPE_BIND_VX_fetch_icache_stage
`define SCOPE_BIND_VX_fetch_warp_sched
`define SCOPE_IO_VX_warp_sched
`define SCOPE_IO_VX_pipeline
`define SCOPE_BIND_VX_pipeline_fetch()
`define SCOPE_BIND_VX_pipeline_fetch
`define SCOPE_IO_VX_core
`define SCOPE_BIND_VX_core_pipeline()
`define SCOPE_BIND_VX_core_pipeline
`define SCOPE_IO_VX_cluster
@@ -33,19 +37,23 @@
`define SCOPE_BIND_Vortex_cluster(__i__)
`define SCOPE_BIND_vortex_afu_vortex()
`define SCOPE_BIND_vortex_afu_vortex
`define SCOPE_IO_VX_lsu_unit
`define SCOPE_IO_VX_gpu_unit
`define SCOPE_IO_VX_execute
`define SCOPE_BIND_VX_execute_lsu_unit()
`define SCOPE_BIND_VX_execute_lsu_unit
`define SCOPE_BIND_VX_pipeline_execute()
`define SCOPE_BIND_VX_execute_gpu_unit
`define SCOPE_BIND_VX_pipeline_execute
`define SCOPE_IO_VX_issue
`define SCOPE_BIND_VX_pipeline_issue()
`define SCOPE_BIND_VX_pipeline_issue
`define SCOPE_IO_VX_bank
@@ -53,19 +61,19 @@
`define SCOPE_BIND_VX_cache_bank(__i__)
`define SCOPE_BIND_Vortex_l3cache()
`define SCOPE_BIND_Vortex_l3cache
`define SCOPE_BIND_VX_cluster_l2cache()
`define SCOPE_BIND_VX_cluster_l2cache
`define SCOPE_IO_VX_mem_unit
`define SCOPE_BIND_VX_mem_unit_dcache()
`define SCOPE_BIND_VX_mem_unit_dcache
`define SCOPE_BIND_VX_core_mem_unit()
`define SCOPE_BIND_VX_core_mem_unit
`define SCOPE_BIND_VX_mem_unit_icache()
`define SCOPE_BIND_VX_mem_unit_icache
`define SCOPE_BIND_VX_mem_unit_smem()
`define SCOPE_BIND_VX_mem_unit_smem
`define SCOPE_DECL_SIGNALS

2
hw/rtl/Vortex.v
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@@ -395,7 +395,7 @@ module Vortex (
.SNP_REQ_TAG_WIDTH (`L3SNP_TAG_WIDTH),
.SNP_FWD_TAG_WIDTH (`L2SNP_TAG_WIDTH)
) l3cache (
`SCOPE_BIND_Vortex_l3cache()
`SCOPE_BIND_Vortex_l3cache
.clk (clk),
.reset (reset),