From 4bfc4ee78ffbf8201042741c84ba5de3200c330e Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 13 Oct 2020 08:44:55 -0700 Subject: [PATCH] scope fixes --- driver/opae/vlsim/Makefile | 18 +++++++++++------- hw/opae/sources_1c.txt | 2 +- hw/opae/vortex_afu.sv | 2 +- hw/rtl/VX_cluster.v | 2 +- hw/rtl/VX_core.v | 4 ++-- hw/rtl/VX_execute.v | 4 ++-- hw/rtl/VX_fetch.v | 4 ++-- hw/rtl/VX_mem_unit.v | 6 +++--- hw/rtl/VX_pipeline.v | 6 +++--- hw/rtl/VX_scope.vh | 34 +++++++++++++++++++++------------- hw/rtl/Vortex.v | 2 +- hw/scripts/scope.json | 2 +- hw/scripts/scope.py | 12 +++++++----- 13 files changed, 56 insertions(+), 42 deletions(-) diff --git a/driver/opae/vlsim/Makefile b/driver/opae/vlsim/Makefile index f6d26d1c..e3b52ec7 100644 --- a/driver/opae/vlsim/Makefile +++ b/driver/opae/vlsim/Makefile @@ -20,8 +20,8 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO #CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 -CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 -#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1 +#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 +CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1 #DEBUG=1 SCOPE=1 @@ -39,6 +39,8 @@ TOP = vortex_afu_shim RTL_DIR=../../../hw/rtl +SCRIPT_DIR=../../../hw/scripts + SRCS = fpga.cpp opae_sim.cpp SRCS += $(RTL_DIR)/fp_cores/svdpi/float_dpi.cpp @@ -67,7 +69,7 @@ endif ifdef SCOPE VL_FLAGS += -DSCOPE CFLAGS += -DSCOPE - SCOPE_CFG = scope + SCOPE_VH = $(RTL_DIR)/scope-defs.vh endif VL_FLAGS += -DNOPAE @@ -80,12 +82,14 @@ PROJECT = libopae-c-vlsim.so all: $(PROJECT) # generate scope data -scope: ../../../hw/scripts/scope.json - ../../../hw/scripts/scope.py $(RTL_INCLUDE) $(CONFIGS) -cc ../scope-defs.h -vl ../../../hw/rtl/scope-defs.vh ../../../hw/scripts/scope.json +scope: $(RTL_DIR)/scope-defs.vh + +$(RTL_DIR)/scope-defs.vh: $(SCRIPT_DIR)/scope.json + $(SCRIPT_DIR)/scope.py $(RTL_INCLUDE) $(CONFIGS) -cc ../scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json -$(PROJECT): $(SRCS) $(SCOPE_CFG) +$(PROJECT): $(SRCS) $(SCOPE_VH) verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT) OPT_FAST="-O0 -g" make -j -C obj_dir -f V$(TOP).mk clean: - rm -rf $(PROJECT) obj_dir ../scope-defs.h ../../../hw/rtl/scope-defs.vh + rm -rf $(PROJECT) obj_dir ../scope-defs.h $(RTL_DIR)/scope-defs.vh diff --git a/hw/opae/sources_1c.txt b/hw/opae/sources_1c.txt index 897468c2..5c63e9cd 100644 --- a/hw/opae/sources_1c.txt +++ b/hw/opae/sources_1c.txt @@ -3,7 +3,7 @@ +define+SYNTHESIS +define+QUARTUS +define+FPU_FAST -#+define+SCOPE ++define+SCOPE #+define+DBG_PRINT_CORE_ICACHE #+define+DBG_PRINT_CORE_DCACHE diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index 3faca262..fff69538 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -954,7 +954,7 @@ end assign cmd_run_done = !vx_busy; Vortex #() vortex ( - `SCOPE_BIND_vortex_afu_vortex() + `SCOPE_BIND_vortex_afu_vortex .clk (clk), .reset (reset | vx_reset), diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index 5f69a8e2..6c899096 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -372,7 +372,7 @@ module VX_cluster #( .SNP_REQ_TAG_WIDTH (`L2SNP_TAG_WIDTH), .SNP_FWD_TAG_WIDTH (`DSNP_TAG_WIDTH) ) l2cache ( - `SCOPE_BIND_VX_cluster_l2cache() + `SCOPE_BIND_VX_cluster_l2cache .clk (clk), .reset (reset), diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index f47eabd8..aa1032a8 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -175,7 +175,7 @@ module VX_core #( VX_pipeline #( .CORE_ID(CORE_ID) ) pipeline ( - `SCOPE_BIND_VX_core_pipeline() + `SCOPE_BIND_VX_core_pipeline .clk(clk), .reset(reset), @@ -251,7 +251,7 @@ module VX_core #( VX_mem_unit #( .CORE_ID(CORE_ID) ) mem_unit ( - `SCOPE_BIND_VX_core_mem_unit() + `SCOPE_BIND_VX_core_mem_unit .clk (clk), .reset (reset), diff --git a/hw/rtl/VX_execute.v b/hw/rtl/VX_execute.v index e56e583c..9586bcd6 100644 --- a/hw/rtl/VX_execute.v +++ b/hw/rtl/VX_execute.v @@ -54,7 +54,7 @@ module VX_execute #( VX_lsu_unit #( .CORE_ID(CORE_ID) ) lsu_unit ( - `SCOPE_BIND_VX_execute_lsu_unit() + `SCOPE_BIND_VX_execute_lsu_unit .clk (clk), .reset (reset), .dcache_req_if (dcache_req_if), @@ -121,7 +121,7 @@ module VX_execute #( VX_gpu_unit #( .CORE_ID(CORE_ID) ) gpu_unit ( - `SCOPE_BIND_VX_execute_gpu_unit() + `SCOPE_BIND_VX_execute_gpu_unit .clk (clk), .reset (reset), .gpu_req_if (gpu_req_if), diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index 1d304ffc..fd3b1fdc 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -29,7 +29,7 @@ module VX_fetch #( VX_warp_sched #( .CORE_ID(CORE_ID) ) warp_sched ( - `SCOPE_BIND_VX_fetch_warp_sched() + `SCOPE_BIND_VX_fetch_warp_sched .clk (clk), .reset (reset), @@ -45,7 +45,7 @@ module VX_fetch #( VX_icache_stage #( .CORE_ID(CORE_ID) ) icache_stage ( - `SCOPE_BIND_VX_fetch_icache_stage() + `SCOPE_BIND_VX_fetch_icache_stage .clk (clk), .reset (reset), diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index ae8fddde..d7a4ffd7 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -77,7 +77,7 @@ module VX_mem_unit # ( .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS), .DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH) ) smem ( - `SCOPE_BIND_VX_mem_unit_smem() + `SCOPE_BIND_VX_mem_unit_smem .clk (clk), .reset (reset), @@ -159,7 +159,7 @@ module VX_mem_unit # ( .DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH), .SNP_REQ_TAG_WIDTH (`DSNP_TAG_WIDTH) ) dcache ( - `SCOPE_BIND_VX_mem_unit_dcache() + `SCOPE_BIND_VX_mem_unit_dcache .clk (clk), .reset (reset), @@ -240,7 +240,7 @@ module VX_mem_unit # ( .CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS), .DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH) ) icache ( - `SCOPE_BIND_VX_mem_unit_icache() + `SCOPE_BIND_VX_mem_unit_icache .clk (clk), .reset (reset), diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 86cd7003..b6a5444c 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -123,7 +123,7 @@ module VX_pipeline #( VX_fetch #( .CORE_ID(CORE_ID) ) fetch ( - `SCOPE_BIND_VX_pipeline_fetch() + `SCOPE_BIND_VX_pipeline_fetch .clk (clk), .reset (reset), .icache_req_if (core_icache_req_if), @@ -150,7 +150,7 @@ module VX_pipeline #( VX_issue #( .CORE_ID(CORE_ID) ) issue ( - `SCOPE_BIND_VX_pipeline_issue() + `SCOPE_BIND_VX_pipeline_issue .clk (clk), .reset (reset), @@ -170,7 +170,7 @@ module VX_pipeline #( VX_execute #( .CORE_ID(CORE_ID) ) execute ( - `SCOPE_BIND_VX_pipeline_execute() + `SCOPE_BIND_VX_pipeline_execute .clk (clk), .reset (reset), diff --git a/hw/rtl/VX_scope.vh b/hw/rtl/VX_scope.vh index 2c007e33..6b58e1a2 100644 --- a/hw/rtl/VX_scope.vh +++ b/hw/rtl/VX_scope.vh @@ -15,15 +15,19 @@ `define SCOPE_IO_VX_fetch -`define SCOPE_BIND_VX_fetch_icache_stage() +`define SCOPE_BIND_VX_fetch_icache_stage + +`define SCOPE_BIND_VX_fetch_warp_sched + +`define SCOPE_IO_VX_warp_sched `define SCOPE_IO_VX_pipeline -`define SCOPE_BIND_VX_pipeline_fetch() +`define SCOPE_BIND_VX_pipeline_fetch `define SCOPE_IO_VX_core -`define SCOPE_BIND_VX_core_pipeline() +`define SCOPE_BIND_VX_core_pipeline `define SCOPE_IO_VX_cluster @@ -33,19 +37,23 @@ `define SCOPE_BIND_Vortex_cluster(__i__) -`define SCOPE_BIND_vortex_afu_vortex() +`define SCOPE_BIND_vortex_afu_vortex `define SCOPE_IO_VX_lsu_unit +`define SCOPE_IO_VX_gpu_unit + `define SCOPE_IO_VX_execute -`define SCOPE_BIND_VX_execute_lsu_unit() +`define SCOPE_BIND_VX_execute_lsu_unit -`define SCOPE_BIND_VX_pipeline_execute() +`define SCOPE_BIND_VX_execute_gpu_unit + +`define SCOPE_BIND_VX_pipeline_execute `define SCOPE_IO_VX_issue -`define SCOPE_BIND_VX_pipeline_issue() +`define SCOPE_BIND_VX_pipeline_issue `define SCOPE_IO_VX_bank @@ -53,19 +61,19 @@ `define SCOPE_BIND_VX_cache_bank(__i__) -`define SCOPE_BIND_Vortex_l3cache() +`define SCOPE_BIND_Vortex_l3cache -`define SCOPE_BIND_VX_cluster_l2cache() +`define SCOPE_BIND_VX_cluster_l2cache `define SCOPE_IO_VX_mem_unit -`define SCOPE_BIND_VX_mem_unit_dcache() +`define SCOPE_BIND_VX_mem_unit_dcache -`define SCOPE_BIND_VX_core_mem_unit() +`define SCOPE_BIND_VX_core_mem_unit -`define SCOPE_BIND_VX_mem_unit_icache() +`define SCOPE_BIND_VX_mem_unit_icache -`define SCOPE_BIND_VX_mem_unit_smem() +`define SCOPE_BIND_VX_mem_unit_smem `define SCOPE_DECL_SIGNALS diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 5e422ed5..914a9232 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -395,7 +395,7 @@ module Vortex ( .SNP_REQ_TAG_WIDTH (`L3SNP_TAG_WIDTH), .SNP_FWD_TAG_WIDTH (`L2SNP_TAG_WIDTH) ) l3cache ( - `SCOPE_BIND_Vortex_l3cache() + `SCOPE_BIND_Vortex_l3cache .clk (clk), .reset (reset), diff --git a/hw/scripts/scope.json b/hw/scripts/scope.json index 8b0ae92b..734fbfb9 100644 --- a/hw/scripts/scope.json +++ b/hw/scripts/scope.json @@ -32,7 +32,7 @@ }, "VX_core": { "submodules": { - "pipeline": {"type":"VX_pipeline", "enabled":false}, + "pipeline": {"type":"VX_pipeline", "enabled":true}, "mem_unit": {"type":"VX_mem_unit", "enabled":true} } }, diff --git a/hw/scripts/scope.py b/hw/scripts/scope.py index 9bedc02c..3cc189a4 100755 --- a/hw/scripts/scope.py +++ b/hw/scripts/scope.py @@ -527,7 +527,7 @@ def gen_vl_header(file, modules, taps): ports[nn] = pp if (0 == scount): - nn = "SCOPE_BIND_" + ntype + '_' + spath + "()" + nn = "SCOPE_BIND_" + ntype + '_' + spath pp = create_signal(nn, ports) for st in new_staps: if e: @@ -746,13 +746,15 @@ struct scope_tap_t { continue paths.pop(-1) parent = -1 + mk = "" for path in paths: - if not path in mdic: + mk += '/' + path + if not mk in mdic: index = len(mdic) - mdic[path] = (index, parent) + mdic[mk] = (path, index, parent) parent = index else: - parent = mdic[path][0] + parent = mdic[mk][1] fdic[key][1] = parent with open(file, 'w') as f: @@ -764,7 +766,7 @@ struct scope_tap_t { m = mdic[key] if i > 0: print(',', file=f) - print("\t{\"" + key + "\", " + str(m[0]) + ", " + str(m[1]) + "}", file=f, end='') + print("\t{\"" + m[0] + "\", " + str(m[1]) + ", " + str(m[2]) + "}", file=f, end='') i += 1 print("", file=f) print("};", file=f)