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Merge remote-tracking branch 'upstream/master' into vortex2

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This commit is contained in:
Hansung Kim
2024-02-01 23:35:58 -08:00
parent a15f4fd483 b31d868a27
commit 48558982f7
203 changed files with 4383 additions and 21981 deletions
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4
hw/rtl/libs/VX_avs_adapter.sv
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@@ -21,8 +21,8 @@ module VX_avs_adapter #(
parameter NUM_BANKS = 1,
parameter TAG_WIDTH = 1,
parameter RD_QUEUE_SIZE = 1,
parameter OUT_REG_REQ = 0,
parameter OUT_REG_RSP = 0
parameter OUT_REG_REQ = 0,
parameter OUT_REG_RSP = 0
) (
input wire clk,
input wire reset,

2
hw/rtl/libs/VX_axi_adapter.sv
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@@ -20,7 +20,7 @@ module VX_axi_adapter #(
parameter TAG_WIDTH = 8,
parameter NUM_BANKS = 1,
parameter AVS_ADDR_WIDTH = (ADDR_WIDTH - `CLOG2(DATA_WIDTH/8)),
parameter OUT_REG_RSP = 0
parameter OUT_REG_RSP = 0
) (
input wire clk,
input wire reset,

4
hw/rtl/libs/VX_fifo_queue.sv
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@@ -201,9 +201,7 @@ module VX_fifo_queue #(
rd_ptr_r <= '0;
rd_ptr_n_r <= 1;
end else begin
if (push) begin
wr_ptr_r <= wr_ptr_r + ADDRW'(1);
end
wr_ptr_r <= wr_ptr_r + ADDRW'(push);
if (pop) begin
rd_ptr_r <= rd_ptr_n_r;
if (DEPTH > 2) begin

4
hw/rtl/libs/VX_mem_adapter.sv
View File

@@ -21,8 +21,8 @@ module VX_mem_adapter #(
parameter DST_ADDR_WIDTH = 1,
parameter SRC_TAG_WIDTH = 1,
parameter DST_TAG_WIDTH = 1,
parameter OUT_REG_REQ = 0,
parameter OUT_REG_RSP = 0
parameter OUT_REG_REQ = 0,
parameter OUT_REG_RSP = 0
) (
input wire clk,
input wire reset,

2
hw/rtl/libs/VX_stream_arb.sv
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@@ -21,7 +21,7 @@ module VX_stream_arb #(
parameter `STRING ARBITER = "P",
parameter LOCK_ENABLE = 1,
parameter MAX_FANOUT = `MAX_FANOUT,
parameter OUT_REG = 0 ,
parameter OUT_REG = 0 ,
parameter NUM_REQS = (NUM_INPUTS + NUM_OUTPUTS - 1) / NUM_OUTPUTS,
parameter LOG_NUM_REQS = `CLOG2(NUM_REQS),
parameter NUM_REQS_W = `UP(LOG_NUM_REQS)

20
hw/rtl/libs/VX_stream_xbar.sv
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@@ -173,25 +173,27 @@ module VX_stream_xbar #(
end
// compute inputs collision
// we have a collision when there exists a valid transfer with mutiple input candicates
// we caount the unique duplicates each cycle.
// we have a collision when there exists a valid transfer with multiple input candicates
// we count the unique duplicates each cycle.
reg [NUM_INPUTS-1:0] per_cycle_collision, per_cycle_collision_r;
wire [`CLOG2(NUM_INPUTS+1)-1:0] collision_count;
reg [PERF_CTR_BITS-1:0] collisions_r;
reg [NUM_INPUTS-1:0] per_cycle_collision;
always @(*) begin
per_cycle_collision = 0;
for (integer i = 0; i < NUM_INPUTS; ++i) begin
for (integer j = 1; j < (NUM_INPUTS-i); ++j) begin
if (valid_in[i] && valid_in[j+i] && sel_in[i] == sel_in[j+i]) begin
per_cycle_collision[i] |= ready_in[i] | ready_in[j+i];
end
per_cycle_collision[i] |= valid_in[i]
&& valid_in[j+i]
&& (sel_in[i] == sel_in[j+i])
&& (ready_in[i] | ready_in[j+i]);
end
end
end
wire [`CLOG2(NUM_INPUTS+1)-1:0] collision_count;
`POP_COUNT(collision_count, per_cycle_collision);
`BUFFER(per_cycle_collision_r, per_cycle_collision);
`POP_COUNT(collision_count, per_cycle_collision_r);
always @(posedge clk) begin
if (reset) begin