259 lines
8.7 KiB
Systemverilog
259 lines
8.7 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_fifo_queue #(
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parameter DATAW = 1,
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parameter DEPTH = 2,
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parameter ALM_FULL = (DEPTH - 1),
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parameter ALM_EMPTY = 1,
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parameter OUT_REG = 0,
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parameter LUTRAM = 1,
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parameter SIZEW = `CLOG2(DEPTH+1)
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) (
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input wire clk,
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input wire reset,
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input wire push,
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input wire pop,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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output wire empty,
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output wire alm_empty,
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output wire full,
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output wire alm_full,
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output wire [SIZEW-1:0] size
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);
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localparam ADDRW = `CLOG2(DEPTH);
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`STATIC_ASSERT(ALM_FULL > 0, ("alm_full must be greater than 0!"))
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`STATIC_ASSERT(ALM_FULL < DEPTH, ("alm_full must be smaller than size!"))
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`STATIC_ASSERT(ALM_EMPTY > 0, ("alm_empty must be greater than 0!"))
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`STATIC_ASSERT(ALM_EMPTY < DEPTH, ("alm_empty must be smaller than size!"))
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`STATIC_ASSERT(`ISPOW2(DEPTH), ("size must be a power of 2!"))
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if (DEPTH == 1) begin
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reg [DATAW-1:0] head_r;
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reg size_r;
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always @(posedge clk) begin
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if (reset) begin
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head_r <= '0;
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size_r <= '0;
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end else begin
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`ASSERT(~push || ~full, ("runtime error: writing to a full queue"));
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`ASSERT(~pop || ~empty, ("runtime error: reading an empty queue"));
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if (push) begin
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if (~pop) begin
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size_r <= 1;
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end
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end else if (pop) begin
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size_r <= '0;
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end
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if (push) begin
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head_r <= data_in;
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end
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end
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end
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assign data_out = head_r;
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assign empty = (size_r == 0);
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assign alm_empty = 1'b1;
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assign full = (size_r != 0);
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assign alm_full = 1'b1;
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assign size = size_r;
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end else begin
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reg empty_r, alm_empty_r;
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reg full_r, alm_full_r;
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reg [ADDRW-1:0] used_r;
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wire [ADDRW-1:0] used_n;
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always @(posedge clk) begin
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if (reset) begin
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empty_r <= 1;
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alm_empty_r <= 1;
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full_r <= 0;
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alm_full_r <= 0;
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used_r <= '0;
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end else begin
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`ASSERT(~(push && ~pop) || ~full, ("runtime error: incrementing full queue"));
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`ASSERT(~(pop && ~push) || ~empty, ("runtime error: decrementing empty queue"));
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if (push) begin
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if (~pop) begin
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empty_r <= 0;
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if (used_r == ADDRW'(ALM_EMPTY))
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alm_empty_r <= 0;
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if (used_r == ADDRW'(DEPTH-1))
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full_r <= 1;
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if (used_r == ADDRW'(ALM_FULL-1))
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alm_full_r <= 1;
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end
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end else if (pop) begin
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full_r <= 0;
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if (used_r == ADDRW'(ALM_FULL))
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alm_full_r <= 0;
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if (used_r == ADDRW'(1))
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empty_r <= 1;
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if (used_r == ADDRW'(ALM_EMPTY+1))
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alm_empty_r <= 1;
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end
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used_r <= used_n;
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end
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end
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if (DEPTH == 2) begin
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assign used_n = used_r ^ (push ^ pop);
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if (0 == OUT_REG) begin
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reg [1:0][DATAW-1:0] shift_reg;
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always @(posedge clk) begin
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if (push) begin
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shift_reg[1] <= shift_reg[0];
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shift_reg[0] <= data_in;
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end
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end
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assign data_out = shift_reg[!used_r[0]];
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end else begin
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reg [DATAW-1:0] data_out_r;
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reg [DATAW-1:0] buffer;
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always @(posedge clk) begin
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if (push) begin
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buffer <= data_in;
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end
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if (push && (empty_r || (used_r && pop))) begin
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data_out_r <= data_in;
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end else if (pop) begin
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data_out_r <= buffer;
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end
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end
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assign data_out = data_out_r;
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end
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end else begin
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assign used_n = $signed(used_r) + ADDRW'($signed(2'(push) - 2'(pop)));
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if (0 == OUT_REG) begin
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reg [ADDRW-1:0] rd_ptr_r;
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reg [ADDRW-1:0] wr_ptr_r;
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always @(posedge clk) begin
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if (reset) begin
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rd_ptr_r <= '0;
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wr_ptr_r <= '0;
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end else begin
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wr_ptr_r <= wr_ptr_r + ADDRW'(push);
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rd_ptr_r <= rd_ptr_r + ADDRW'(pop);
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end
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end
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VX_dp_ram #(
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.DATAW (DATAW),
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.SIZE (DEPTH),
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.LUTRAM (LUTRAM)
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) dp_ram (
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.clk(clk),
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.read (1'b1),
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.write (push),
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`UNUSED_PIN (wren),
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.waddr (wr_ptr_r),
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.wdata (data_in),
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.raddr (rd_ptr_r),
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.rdata (data_out)
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);
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end else begin
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wire [DATAW-1:0] dout;
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reg [DATAW-1:0] dout_r;
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reg [ADDRW-1:0] wr_ptr_r;
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reg [ADDRW-1:0] rd_ptr_r;
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reg [ADDRW-1:0] rd_ptr_n_r;
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always @(posedge clk) begin
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if (reset) begin
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wr_ptr_r <= '0;
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rd_ptr_r <= '0;
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rd_ptr_n_r <= 1;
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end else begin
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wr_ptr_r <= wr_ptr_r + ADDRW'(push);
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if (pop) begin
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rd_ptr_r <= rd_ptr_n_r;
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if (DEPTH > 2) begin
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rd_ptr_n_r <= rd_ptr_r + ADDRW'(2);
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end else begin // (DEPTH == 2);
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rd_ptr_n_r <= ~rd_ptr_n_r;
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end
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end
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end
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end
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wire going_empty;
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if (ALM_EMPTY == 1) begin
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assign going_empty = alm_empty_r;
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end else begin
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assign going_empty = (used_r == ADDRW'(1));
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end
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VX_dp_ram #(
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.DATAW (DATAW),
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.SIZE (DEPTH),
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.LUTRAM (LUTRAM)
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) dp_ram (
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.clk (clk),
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.read (1'b1),
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.write (push),
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`UNUSED_PIN (wren),
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.waddr (wr_ptr_r),
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.wdata (data_in),
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.raddr (rd_ptr_n_r),
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.rdata (dout)
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);
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always @(posedge clk) begin
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if (push && (empty_r || (going_empty && pop))) begin
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dout_r <= data_in;
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end else if (pop) begin
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dout_r <= dout;
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end
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end
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assign data_out = dout_r;
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end
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end
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assign empty = empty_r;
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assign alm_empty = alm_empty_r;
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assign full = full_r;
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assign alm_full = alm_full_r;
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assign size = {full_r, used_r};
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end
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endmodule
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`TRACING_ON
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