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using single-port block ram for cache tags, restoring core reset signal

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Blaise Tine
2021-01-02 19:53:41 -08:00
parent a766c16ac9
commit 4815ab099c
9 changed files with 213 additions and 23 deletions
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10
hw/simulate/simulator.cpp
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@@ -3,6 +3,8 @@
#include <fstream>
#include <iomanip>
#define RESET_DELAY 1
#define ENABLE_DRAM_STALLS
#define DRAM_LATENCY 24
#define DRAM_RQ_SIZE 16
@@ -81,8 +83,7 @@ void Simulator::reset() {
vortex_->reset = 0;
// Turn on assertion after reset
Verilated::assertOn(true);
reset_time_ = timestamp;
}
void Simulator::step() {
@@ -99,6 +100,11 @@ void Simulator::step() {
this->eval_dram_bus();
this->eval_io_bus();
this->eval_csr_bus();
if ((timestamp - reset_time_) == (RESET_DELAY*2)) {
// Turn on assertion after reset
Verilated::assertOn(true);
}
#ifndef NDEBUG
fflush(stdout);