diff --git a/driver/opae/vlsim/opae_sim.cpp b/driver/opae/vlsim/opae_sim.cpp index 34c2a4c6..c55cce88 100644 --- a/driver/opae/vlsim/opae_sim.cpp +++ b/driver/opae/vlsim/opae_sim.cpp @@ -8,6 +8,8 @@ #define CCI_RQ_SIZE 16 #define CCI_WQ_SIZE 16 +#define RESET_DELAY 1 + #define ENABLE_DRAM_STALLS #define DRAM_LATENCY 24 #define DRAM_RQ_SIZE 16 @@ -137,9 +139,8 @@ void opae_sim::reset() { this->eval(); vortex_afu_->reset = 0; - - // Turn on assertion after reset - Verilated::assertOn(true); + + reset_time_ = timestamp; } void opae_sim::step() { @@ -153,6 +154,11 @@ void opae_sim::step() { vortex_afu_->clk = 1; this->eval(); + if ((timestamp - reset_time_) == (RESET_DELAY*2)) { + // Turn on assertion after reset + Verilated::assertOn(true); + } + #ifndef NDEBUG fflush(stdout); #endif diff --git a/driver/opae/vlsim/opae_sim.h b/driver/opae/vlsim/opae_sim.h index ad08019e..b3b9e37f 100644 --- a/driver/opae/vlsim/opae_sim.h +++ b/driver/opae/vlsim/opae_sim.h @@ -85,6 +85,8 @@ private: std::mutex mutex_; + uint64_t reset_time_; + RAM ram_; Vvortex_afu_shim *vortex_afu_; #ifdef VCD_OUTPUT diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index e4803572..4d416efe 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -68,13 +68,19 @@ module VX_cluster #( wire [`NUM_CORES-1:0] per_core_ebreak; for (genvar i = 0; i < `NUM_CORES; i++) begin + + reg core_reset; + always @(posedge clk) begin + core_reset <= reset; + end + VX_core #( .CORE_ID(i + (CLUSTER_ID * `NUM_CORES)) ) core ( `SCOPE_BIND_VX_cluster_core(i) .clk (clk), - .reset (reset), + .reset (core_reset), .dram_req_valid (per_core_dram_req_valid[i]), .dram_req_rw (per_core_dram_req_rw [i]), diff --git a/hw/rtl/cache/VX_miss_resrv.v b/hw/rtl/cache/VX_miss_resrv.v index c5356ef5..ff6a358f 100644 --- a/hw/rtl/cache/VX_miss_resrv.v +++ b/hw/rtl/cache/VX_miss_resrv.v @@ -132,8 +132,9 @@ module VX_miss_resrv #( VX_dp_ram #( .DATAW(`MSHR_DATA_WIDTH), .SIZE(MSHR_SIZE), - .RWCHECK(1) - ) datatable ( + .RWCHECK(1), + .FASTRAM(1) + ) entries ( .clk(clk), .waddr(tail_ptr), .raddr(schedule_ptr), diff --git a/hw/rtl/cache/VX_tag_access.v b/hw/rtl/cache/VX_tag_access.v index 64e016b6..8f625e22 100644 --- a/hw/rtl/cache/VX_tag_access.v +++ b/hw/rtl/cache/VX_tag_access.v @@ -65,7 +65,8 @@ module VX_tag_access #( .clk (clk), .reset (reset), - .read_addr (addrline), + .addr (addrline), + .read_valid (read_valid), .read_dirty (read_dirty), .read_tag (read_tag), @@ -73,7 +74,6 @@ module VX_tag_access #( .do_fill (do_fill), .do_write (do_write), .invalidate (do_invalidate), - .write_addr (addrline), .write_tag (addrtag) ); diff --git a/hw/rtl/cache/VX_tag_store.v b/hw/rtl/cache/VX_tag_store.v index 7d9898cc..6965b104 100644 --- a/hw/rtl/cache/VX_tag_store.v +++ b/hw/rtl/cache/VX_tag_store.v @@ -15,13 +15,13 @@ module VX_tag_store #( input wire clk, input wire reset, + input wire[`LINE_SELECT_BITS-1:0] addr, + input wire do_fill, input wire do_write, - input wire invalidate, - input wire[`LINE_SELECT_BITS-1:0] write_addr, + input wire invalidate, input wire[`TAG_SELECT_BITS-1:0] write_tag, - input wire[`LINE_SELECT_BITS-1:0] read_addr, output wire[`TAG_SELECT_BITS-1:0] read_tag, output wire read_valid, output wire read_dirty @@ -37,25 +37,23 @@ module VX_tag_store #( end end else begin if (do_fill) begin - valid[write_addr] <= 1; - dirty[write_addr] <= 0; + valid[addr] <= 1; + dirty[addr] <= 0; end else if (do_write) begin - dirty[write_addr] <= 1; + dirty[addr] <= 1; end else if (invalidate) begin - valid[write_addr] <= 0; + valid[addr] <= 0; end end end - VX_dp_ram #( + VX_sp_ram #( .DATAW(`TAG_SELECT_BITS), .SIZE(`LINES_PER_BANK), - .FASTRAM(1), .RWCHECK(1) ) tags ( .clk(clk), - .waddr(write_addr), - .raddr(read_addr), + .addr(addr), .wren(do_fill), .byteen(1'b1), .rden(1'b1), @@ -63,7 +61,7 @@ module VX_tag_store #( .dout(read_tag) ); - assign read_valid = valid[read_addr]; - assign read_dirty = dirty[read_addr]; + assign read_valid = valid[addr]; + assign read_dirty = dirty[addr]; endmodule diff --git a/hw/rtl/libs/VX_sp_ram.v b/hw/rtl/libs/VX_sp_ram.v new file mode 100644 index 00000000..37974096 --- /dev/null +++ b/hw/rtl/libs/VX_sp_ram.v @@ -0,0 +1,169 @@ +`include "VX_platform.vh" + +`TRACING_OFF +module VX_sp_ram #( + parameter DATAW = 1, + parameter SIZE = 1, + parameter BYTEENW = 1, + parameter BUFFERED = 0, + parameter RWCHECK = 1, + parameter ADDRW = $clog2(SIZE), + parameter SIZEW = $clog2(SIZE+1), + parameter FASTRAM = 0 +) ( + input wire clk, + input wire [ADDRW-1:0] addr, + input wire wren, + input wire [BYTEENW-1:0] byteen, + input wire rden, + input wire [DATAW-1:0] din, + output wire [DATAW-1:0] dout +); + + `STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter")) + + localparam DATA32W = DATAW / 32; + localparam BYTEEN32W = BYTEENW / 4; + + if (FASTRAM) begin + if (BUFFERED) begin + reg [DATAW-1:0] dout_r; + + if (BYTEENW > 1) begin + `USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0]; + + always @(posedge clk) begin + if (wren) begin + for (integer j = 0; j < BYTEEN32W; j++) begin + for (integer i = 0; i < 4; i++) begin + if (byteen[j * 4 + i]) + mem[addr][j][i] <= din[j * 32 + i * 8 +: 8]; + end + end + end + if (rden) + dout_r <= mem[addr]; + end + end else begin + `USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; + + always @(posedge clk) begin + if (wren && byteen) + mem[addr] <= din; + if (rden) + dout_r <= mem[addr]; + end + end + assign dout = dout_r; + end else begin + `UNUSED_VAR (rden) + if (BYTEENW > 1) begin + `USE_FAST_BRAM reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0]; + + always @(posedge clk) begin + if (wren) begin + for (integer j = 0; j < BYTEEN32W; j++) begin + for (integer i = 0; i < 4; i++) begin + if (byteen[j * 4 + i]) + mem[addr][j][i] <= din[j * 32 + i * 8 +: 8]; + end + end + end + end + assign dout = mem[addr]; + end else begin + `USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0]; + + always @(posedge clk) begin + if (wren && byteen) + mem[addr] <= din; + end + assign dout = mem[addr]; + end + end + end else begin + if (BUFFERED) begin + reg [DATAW-1:0] dout_r; + + if (BYTEENW > 1) begin + reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0]; + + always @(posedge clk) begin + if (wren) begin + for (integer j = 0; j < BYTEEN32W; j++) begin + for (integer i = 0; i < 4; i++) begin + if (byteen[j * 4 + i]) + mem[addr][j][i] <= din[j * 32 + i * 8 +: 8]; + end + end + end + if (rden) + dout_r <= mem[addr]; + end + end else begin + reg [DATAW-1:0] mem [SIZE-1:0]; + + always @(posedge clk) begin + if (wren && byteen) + mem[addr] <= din; + if (rden) + dout_r <= mem[addr]; + end + end + assign dout = dout_r; + end else begin + `UNUSED_VAR (rden) + if (RWCHECK) begin + if (BYTEENW > 1) begin + reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0]; + + always @(posedge clk) begin + if (wren) begin + for (integer j = 0; j < BYTEEN32W; j++) begin + for (integer i = 0; i < 4; i++) begin + if (byteen[j * 4 + i]) + mem[addr][j][i] <= din[j * 32 + i * 8 +: 8]; + end + end + end + end + assign dout = mem[addr]; + end else begin + reg [DATAW-1:0] mem [SIZE-1:0]; + + always @(posedge clk) begin + if (wren && byteen) + mem[addr] <= din; + end + assign dout = mem[addr]; + end + end else begin + if (BYTEENW > 1) begin + `NO_RW_RAM_CHECK reg [DATA32W-1:0][3:0][7:0] mem [SIZE-1:0]; + + always @(posedge clk) begin + if (wren) begin + for (integer j = 0; j < BYTEEN32W; j++) begin + for (integer i = 0; i < 4; i++) begin + if (byteen[j * 4 + i]) + mem[addr][j][i] <= din[j * 32 + i * 8 +: 8]; + end + end + end + end + assign dout = mem[addr]; + end else begin + `NO_RW_RAM_CHECK reg [DATAW-1:0] mem [SIZE-1:0]; + + always @(posedge clk) begin + if (wren && byteen) + mem[addr] <= din; + end + assign dout = mem[addr]; + end + end + end + end + +endmodule +`TRACING_ON \ No newline at end of file diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index dff4bbd5..a16b066d 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -3,6 +3,8 @@ #include #include +#define RESET_DELAY 1 + #define ENABLE_DRAM_STALLS #define DRAM_LATENCY 24 #define DRAM_RQ_SIZE 16 @@ -81,8 +83,7 @@ void Simulator::reset() { vortex_->reset = 0; - // Turn on assertion after reset - Verilated::assertOn(true); + reset_time_ = timestamp; } void Simulator::step() { @@ -99,6 +100,11 @@ void Simulator::step() { this->eval_dram_bus(); this->eval_io_bus(); this->eval_csr_bus(); + + if ((timestamp - reset_time_) == (RESET_DELAY*2)) { + // Turn on assertion after reset + Verilated::assertOn(true); + } #ifndef NDEBUG fflush(stdout); diff --git a/hw/simulate/simulator.h b/hw/simulate/simulator.h index 626474bd..181d5615 100644 --- a/hw/simulate/simulator.h +++ b/hw/simulate/simulator.h @@ -69,6 +69,8 @@ private: bool csr_req_active_; uint32_t* csr_rsp_value_; + uint64_t reset_time_; + RAM *ram_; VVortex *vortex_; #ifdef VCD_OUTPUT