using single-port block ram for cache tags, restoring core reset signal

2021-01-02 19:53:41 -08:00
parent a766c16ac9
commit 4815ab099c
9 changed files with 213 additions and 23 deletions
--- a/hw/rtl/cache/VX_miss_resrv.v
+++ b/hw/rtl/cache/VX_miss_resrv.v
@@ -132,8 +132,9 @@ module VX_miss_resrv #(
    VX_dp_ram #(
        .DATAW(`MSHR_DATA_WIDTH),
        .SIZE(MSHR_SIZE),
-        .RWCHECK(1)
-    ) datatable (
+        .RWCHECK(1),
+        .FASTRAM(1)
+    ) entries (
        .clk(clk),
        .waddr(tail_ptr),                                
        .raddr(schedule_ptr),