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using single-port block ram for cache tags, restoring core reset signal

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This commit is contained in:
Blaise Tine
2021-01-02 19:53:41 -08:00
parent a766c16ac9
commit 4815ab099c
9 changed files with 213 additions and 23 deletions
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5
hw/rtl/cache/VX_miss_resrv.v vendored
View File

@@ -132,8 +132,9 @@ module VX_miss_resrv #(
VX_dp_ram #(
.DATAW(`MSHR_DATA_WIDTH),
.SIZE(MSHR_SIZE),
.RWCHECK(1)
) datatable (
.RWCHECK(1),
.FASTRAM(1)
) entries (
.clk(clk),
.waddr(tail_ptr),
.raddr(schedule_ptr),

4
hw/rtl/cache/VX_tag_access.v vendored
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@@ -65,7 +65,8 @@ module VX_tag_access #(
.clk (clk),
.reset (reset),
.read_addr (addrline),
.addr (addrline),
.read_valid (read_valid),
.read_dirty (read_dirty),
.read_tag (read_tag),
@@ -73,7 +74,6 @@ module VX_tag_access #(
.do_fill (do_fill),
.do_write (do_write),
.invalidate (do_invalidate),
.write_addr (addrline),
.write_tag (addrtag)
);

24
hw/rtl/cache/VX_tag_store.v vendored
View File

@@ -15,13 +15,13 @@ module VX_tag_store #(
input wire clk,
input wire reset,
input wire[`LINE_SELECT_BITS-1:0] addr,
input wire do_fill,
input wire do_write,
input wire invalidate,
input wire[`LINE_SELECT_BITS-1:0] write_addr,
input wire invalidate,
input wire[`TAG_SELECT_BITS-1:0] write_tag,
input wire[`LINE_SELECT_BITS-1:0] read_addr,
output wire[`TAG_SELECT_BITS-1:0] read_tag,
output wire read_valid,
output wire read_dirty
@@ -37,25 +37,23 @@ module VX_tag_store #(
end
end else begin
if (do_fill) begin
valid[write_addr] <= 1;
dirty[write_addr] <= 0;
valid[addr] <= 1;
dirty[addr] <= 0;
end else if (do_write) begin
dirty[write_addr] <= 1;
dirty[addr] <= 1;
end else if (invalidate) begin
valid[write_addr] <= 0;
valid[addr] <= 0;
end
end
end
VX_dp_ram #(
VX_sp_ram #(
.DATAW(`TAG_SELECT_BITS),
.SIZE(`LINES_PER_BANK),
.FASTRAM(1),
.RWCHECK(1)
) tags (
.clk(clk),
.waddr(write_addr),
.raddr(read_addr),
.addr(addr),
.wren(do_fill),
.byteen(1'b1),
.rden(1'b1),
@@ -63,7 +61,7 @@ module VX_tag_store #(
.dout(read_tag)
);
assign read_valid = valid[read_addr];
assign read_dirty = dirty[read_addr];
assign read_valid = valid[addr];
assign read_dirty = dirty[addr];
endmodule