Added Snoop Invalidate/Writeback Req type
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@@ -16,6 +16,7 @@ module VX_cache_dram_req_arb (
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input wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req,
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input wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr,
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input wire[`NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data,
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input wire[`NUMBER_BANKS-1:0] per_bank_dram_because_of_snp,
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// real Dram request
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output wire dram_req,
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@@ -23,7 +24,8 @@ module VX_cache_dram_req_arb (
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output wire dram_req_read,
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output wire [31:0] dram_req_addr,
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output wire [31:0] dram_req_size,
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output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data
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output wire [`BANK_LINE_SIZE_RNG][31:0] dram_req_data,
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output wire dram_req_because_of_wb
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);
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@@ -47,10 +49,11 @@ module VX_cache_dram_req_arb (
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);
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wire dwb_valid;
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wire dwb_valid;
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wire[`vx_clog2(`NUMBER_BANKS)-1:0] dwb_bank;
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wire[`NUMBER_BANKS-1:0] use_wb_valid = per_bank_dram_wb_req | per_bank_dram_because_of_snp;
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VX_generic_priority_encoder #(.N(`NUMBER_BANKS)) VX_sel_dwb(
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.valids(per_bank_dram_wb_req),
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.valids(use_wb_valid),
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.index (dwb_bank),
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.found (dwb_valid)
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);
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@@ -59,11 +62,12 @@ module VX_cache_dram_req_arb (
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assign per_bank_dram_wb_queue_pop = per_bank_dram_wb_req & (~(1 << dwb_bank));
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assign dram_req = dwb_valid || dfqq_req;
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assign dram_req_write = dwb_valid;
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assign dram_req_read = dfqq_req && !dwb_valid;
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assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK;
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assign dram_req_size = `BANK_LINE_SIZE_BYTES;
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assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;
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assign dram_req = dwb_valid || dfqq_req;
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assign dram_req_write = dwb_valid;
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assign dram_req_read = dfqq_req && !dwb_valid;
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assign dram_req_addr = (dwb_valid ? per_bank_dram_wb_req_addr[dwb_bank] : dfqq_req_addr) & `BASE_ADDR_MASK;
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assign dram_req_size = `BANK_LINE_SIZE_BYTES;
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assign dram_req_data = dwb_valid ? per_bank_dram_wb_req_data[dwb_bank] : 0;
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assign dram_req_because_of_wb = dwb_valid ? per_bank_dram_because_of_snp[dwb_bank] : 0;
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endmodule
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