scope fixes
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@@ -9,6 +9,7 @@ module VX_scope #(
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input wire clk,
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input wire reset,
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input wire start,
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input wire stop,
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input wire [DATAW-1:0] data_in,
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input wire [BUSW-1:0] bus_in,
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output reg [BUSW-1:0] bus_out,
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@@ -21,7 +22,7 @@ module VX_scope #(
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CMD_GET_VALID,
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CMD_GET_DATA,
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CMD_GET_WIDTH,
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CMD_GET_DEPTH,
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CMD_GET_COUNT,
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CMD_SET_DELAY,
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CMD_SET_DURATION,
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CMD_SET_RESERVED1,
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@@ -32,7 +33,7 @@ module VX_scope #(
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GET_VALID,
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GET_DATA,
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GET_WIDTH,
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GET_DEPTH
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GET_COUNT
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} cmd_get_t;
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reg [DATAW-1:0] data_store [SIZE-1:0];
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@@ -78,7 +79,7 @@ module VX_scope #(
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CMD_GET_VALID,
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CMD_GET_DATA,
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CMD_GET_WIDTH,
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CMD_GET_DEPTH: out_cmd <= $bits(out_cmd)'(cmd_type);
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CMD_GET_COUNT: out_cmd <= $bits(out_cmd)'(cmd_type);
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CMD_SET_DELAY: delay_val <= $bits(delay_val)'(cmd_data);
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CMD_SET_DURATION: waddr_end <= $bits(waddr)'(cmd_data);
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default:;
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@@ -101,7 +102,8 @@ module VX_scope #(
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if (start_wait) begin
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delay_cntr <= delay_cntr - 1;
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if (1 == delay_cntr) begin
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if (1 == delay_cntr) begin
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$display("%t: scope-state: recording", $time);
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start_wait <= 0;
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recording <= 1;
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delta <= 0;
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@@ -125,10 +127,13 @@ module VX_scope #(
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waddr <= waddr + 1;
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end
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if (waddr == waddr_end) begin
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if (stop
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|| (waddr == waddr_end)) begin
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$display("%t: scope-state: data_valid, waddr=%0d", $time, waddr);
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waddr <= waddr; // keep last written address
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recording <= 0;
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data_valid <= 1;
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read_delta <= DELTA_ENABLE;
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read_delta <= DELTA_ENABLE;
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end
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end
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@@ -145,14 +150,14 @@ module VX_scope #(
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raddr <= raddr + 1;
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read_offset <= 0;
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read_delta <= DELTA_ENABLE;
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if (raddr == waddr_end) begin
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if (raddr == waddr) begin
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data_valid <= 0;
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end
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end
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end else begin
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raddr <= raddr + 1;
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read_delta <= DELTA_ENABLE;
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if (raddr == waddr_end) begin
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if (raddr == waddr) begin
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data_valid <= 0;
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end
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end
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@@ -165,7 +170,7 @@ module VX_scope #(
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case (out_cmd)
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GET_VALID : bus_out = BUSW'(data_valid);
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GET_WIDTH : bus_out = BUSW'(DATAW);
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GET_DEPTH : bus_out = BUSW'(waddr_end) + BUSW'(1);
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GET_COUNT : bus_out = BUSW'(waddr) + BUSW'(1);
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default : bus_out = read_delta ? (BUSW)'(delta_store[raddr]) : (BUSW)'(data_store[raddr] >> read_offset);
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endcase
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end
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@@ -175,8 +180,8 @@ module VX_scope #(
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if (bus_read) begin
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$display("%t: scope-read: cmd=%0d, out=0x%0h, addr=%0d, off=%0d", $time, out_cmd, bus_out, raddr, read_offset);
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end
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if (DELTA_ENABLE && recording && (trigger_id != prev_id) && (delta != 0)) begin
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$display("%t: scope-write: waddr=%0d, delta=%0d", $time, waddr, delta);
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if (bus_write) begin
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$display("%t: scope-write: cmd=%0d, value=%0d", $time, cmd_type, cmd_data);
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end
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end
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`endif
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