From 457783322b0bcd987c8c683b81e23e711a2923e3 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 9 Jun 2020 07:03:52 -0700 Subject: [PATCH] scope fixes --- driver/opae/vortex.cpp | 93 +++++++++++++++++----------- driver/rtlsim/Makefile | 2 +- driver/tests/basic/common.h | 2 +- driver/tests/basic/kernel.bin | Bin 6556 -> 6804 bytes hw/opae/sources.txt | 19 +++--- hw/opae/vortex_afu.sv | 16 ++++- hw/rtl/VX_define.vh | 52 ++++++++++++---- hw/rtl/VX_dram_arb.v | 68 ++++++++++---------- hw/rtl/VX_pipeline.v | 22 ++++--- hw/rtl/Vortex.v | 8 ++- hw/rtl/Vortex_Cluster.v | 56 +++++++++-------- hw/rtl/Vortex_Socket.v | 19 +++--- hw/rtl/libs/VX_scope.v | 27 ++++---- hw/syn/quartus/pipeline/Makefile | 70 +++++++++++++++++++++ hw/syn/quartus/pipeline/project.sdc | 9 +++ hw/syn/quartus/pipeline/project.tcl | 41 ++++++++++++ 16 files changed, 349 insertions(+), 155 deletions(-) create mode 100644 hw/syn/quartus/pipeline/Makefile create mode 100644 hw/syn/quartus/pipeline/project.sdc create mode 100644 hw/syn/quartus/pipeline/project.tcl diff --git a/driver/opae/vortex.cpp b/driver/opae/vortex.cpp index 7a7d23a1..f2a6fb23 100755 --- a/driver/opae/vortex.cpp +++ b/driver/opae/vortex.cpp @@ -67,12 +67,19 @@ inline bool is_aligned(size_t addr, size_t alignment) { /////////////////////////////////////////////////////////////////////////////// -static int vx_scope_trace(vx_device_h hdevice) { +static int vx_scope_start(vx_device_h hdevice) { if (nullptr == hdevice) return -1; vx_device_t *device = ((vx_device_t*)hdevice); + // set start delay + uint64_t delay = ((0 << 3) | 4); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, delay)); + + // start execution + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_RUN)); + std::ofstream ofs("vx_scope.vcd"); ofs << "$timescale 1 ns $end" << std::endl; @@ -99,30 +106,24 @@ static int vx_scope_trace(vx_device_h hdevice) { fwidth += 19; - ofs << "$var reg 2 14 icache_req_tag $end" << std::endl; - ofs << "$var reg 2 15 icache_rsp_tag $end" << std::endl; - ofs << "$var reg 2 16 dcache_req_tag $end" << std::endl; - ofs << "$var reg 2 17 dcache_rsp_tag $end" << std::endl; - ofs << "$var reg 29 18 dram_req_tag $end" << std::endl; - ofs << "$var reg 29 19 dram_rsp_tag $end" << std::endl; + ofs << "$var reg 32 14 icache_req_addr $end" << std::endl; + ofs << "$var reg 2 15 icache_req_tag $end" << std::endl; + ofs << "$var reg 32 16 icache_rsp_data $end" << std::endl; + ofs << "$var reg 2 17 icache_rsp_tag $end" << std::endl; + ofs << "$var reg 2 18 dcache_req_tag $end" << std::endl; + ofs << "$var reg 2 19 dcache_rsp_tag $end" << std::endl; + ofs << "$var reg 29 20 dram_req_tag $end" << std::endl; + ofs << "$var reg 29 21 dram_rsp_tag $end" << std::endl; - fwidth += 66; + fwidth += 128; - const int num_signals = 20; + #define IS_PC_SID(x) (x == 14) - ofs << "enddefinitions $end" << std::endl; + const int num_signals = 22; uint64_t frame_width, max_frames, data_valid; - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 2)); - CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_DATA, &frame_width)); - std::cout << "scope::frame_width=" << frame_width << std::endl; - - assert((fwidth-1)== (int)frame_width); - - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 3)); - CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_DATA, &max_frames)); - std::cout << "scope::max_frames=" << max_frames << std::endl; + ofs << "enddefinitions $end" << std::endl; do { CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 0)); @@ -132,7 +133,17 @@ static int vx_scope_trace(vx_device_h hdevice) { std::this_thread::sleep_for(std::chrono::milliseconds(1)); } while (true); - std::cout << "scope trace dump begin..." << std::endl; + std::cout << "scope trace dump begin..." << std::endl; + + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 2)); + CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_DATA, &frame_width)); + std::cout << "scope::frame_width=" << frame_width << std::endl; + + assert((fwidth-1)== (int)frame_width); + + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 3)); + CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_DATA, &max_frames)); + std::cout << "scope::max_frames=" << max_frames << std::endl; CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 1)); @@ -175,7 +186,12 @@ static int vx_scope_trace(vx_device_h hdevice) { if (signal_offset == signal_width) { signa_data[signal_width] = 0; // string null termination - ofs << 'b' << signa_data.data() << ' ' << (num_signals - signal_id) << std::endl; + int sid = (num_signals - signal_id); + if (IS_PC_SID(sid)) { + ofs << 'b' << signa_data.data() << "00 " << sid << std::endl; + } else { + ofs << 'b' << signa_data.data() << ' ' << sid << std::endl; + } signal_offset = 0; ++signal_id; } @@ -207,22 +223,28 @@ static int vx_scope_trace(vx_device_h hdevice) { do { switch (num_signals - signal_id) { - case 14: + default: + print_signal(word, 1); + break; case 15: - case 16: case 17: + case 18: + case 19: print_signal(word, 2); break; case 5: case 7: print_signal(word, 4); break; - case 18: - case 19: + case 20: + case 21: print_signal(word, 29); break; - default: - print_signal(word, 1); + case 14: + print_signal(word, 30); + break; + case 16: + print_signal(word, 32); break; } } while ((frame_offset % 64) != 0); @@ -561,19 +583,20 @@ extern int vx_flush_caches(vx_device_h hdevice, size_t dev_maddr, size_t size) { extern int vx_start(vx_device_h hdevice) { if (nullptr == hdevice) - return -1; - - vx_device_t *device = ((vx_device_t*)hdevice); + return -1; // Ensure ready for new command if (vx_ready_wait(hdevice, -1) != 0) return -1; - - // start execution - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_RUN)); - + #ifdef SCOPE - vx_scope_trace(hdevice); + int ret = vx_scope_start(hdevice); + if (ret != 0) + return ret; +#else + // start execution + vx_device_t *device = ((vx_device_t*)hdevice); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_RUN)); #endif return 0; diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 35c0aa17..658e089f 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -19,7 +19,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ #MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #DEBUG=1 -AFU=1 +#AFU=1 CFLAGS += -fPIC diff --git a/driver/tests/basic/common.h b/driver/tests/basic/common.h index 69bd8c1c..b60e40f1 100644 --- a/driver/tests/basic/common.h +++ b/driver/tests/basic/common.h @@ -3,6 +3,6 @@ #define DEV_MEM_SRC_ADDR 0x10000040 #define DEV_MEM_DST_ADDR 0x20000080 -#define NUM_BLOCKS 64 +#define NUM_BLOCKS 1 #endif \ No newline at end of file diff --git a/driver/tests/basic/kernel.bin b/driver/tests/basic/kernel.bin index cdd3dcc0bde6f3935f75856eca286890f4fe5168..6efd60e551274b6b3689dc81c48c103b7ea96eef 100644 GIT binary patch delta 637 zcmZ|NPixdb7zXes$xJeVig5?hRaCZ3v#y1r5Nx2Q9MrA19t6>Y6auNx!zv4U+$>>J zukvcwLl33cdhr&D9z1jlf?q)W4qlcb_~%q7i*;e41H%h5KL+0SnXTaEjZU8f)azYp z`>Xo8vyUOti;_E72Z!tp4rM+#49vZVlp6v|)2d2-YhF2ji0GQCXaRMpX~$mu9K5-% zatAfZcv)wNrwBgn>V@@2j~{MVXfs4;!3oT7FdAluWsTb`G*K(eukf}_+uLz%G9AR? zi$nP|Xmb&PP}mbJ^OjlZq^K#I2yf@9h#5ai`IS@L^|1p#LwPviIwucCV>rca%9|7L z#I1~-;1=cgPI0Sa$2g~a?Z3+!%gktqQ6pYQbz62FSN3(3fmY1~Alk)u^?#RK;ci@pB6yN2(%OXd#^{&!vi}jIZsl=w$7f2 p?u^L9Rkb+K-&Lv~H1#F^t-I%uepGwz0#bUyUl&z3HP|B;>0el^p#=Z{ delta 316 zcmYk%u}Z^G6b9fwH}@t)P}1JoRD@8B3W{4OUE?6WfV3zMO2-Zgu7VM1Gs_Wl$RI*n z_n@wA38+ut12}XM;vkBP_14J)hky9L;hc*~?4Mi;fLa?fM@xIGY2P73FfE0RCIn<_ zFqG}V&^NjPDVL$Y>Zp`L%qv&SfO3Wq2j~~2rj5Pj9K6L-<-(lgVv>0>QBEFv%oiW5 zvGvZYCYUrM_|XUt1}Zi=75HWk)HZk$y+AruR1MgA$HZA@6N&K&@4Cw=is0Sc^Vh=H z58Y}m6D~bzuC`7iZEWy5MP{Ae*p8dlr1f0$t?%IPo`rMB?UkSbi%Fi=DAr4KtWOmu m%&Je=|2m2FG+#)ezEZPWLYS&un?p$Z##LfFq0SFy5&i> read_offset); endcase end @@ -175,8 +180,8 @@ module VX_scope #( if (bus_read) begin $display("%t: scope-read: cmd=%0d, out=0x%0h, addr=%0d, off=%0d", $time, out_cmd, bus_out, raddr, read_offset); end - if (DELTA_ENABLE && recording && (trigger_id != prev_id) && (delta != 0)) begin - $display("%t: scope-write: waddr=%0d, delta=%0d", $time, waddr, delta); + if (bus_write) begin + $display("%t: scope-write: cmd=%0d, value=%0d", $time, cmd_type, cmd_data); end end `endif diff --git a/hw/syn/quartus/pipeline/Makefile b/hw/syn/quartus/pipeline/Makefile new file mode 100644 index 00000000..b1ceee0c --- /dev/null +++ b/hw/syn/quartus/pipeline/Makefile @@ -0,0 +1,70 @@ +PROJECT = VX_pipeline +TOP_LEVEL_ENTITY = VX_pipeline +SRC_FILE = VX_pipeline.v +PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf + +# Part, Family +FAMILY = "Arria 10" +DEVICE = 10AX115N3F40E2SG + +# Executable Configuration +SYN_ARGS = --parallel --read_settings_files=on +FIT_ARGS = --part=$(DEVICE) --read_settings_files=on +ASM_ARGS = +STA_ARGS = --do_report_timing + +# Build targets +all: $(PROJECT).sta.rpt + +syn: $(PROJECT).syn.rpt + +fit: $(PROJECT).fit.rpt + +asm: $(PROJECT).asm.rpt + +sta: $(PROJECT).sta.rpt + +smart: smart.log + +# Target implementations +STAMP = echo done > + +$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) + quartus_syn $(PROJECT) $(SYN_ARGS) + $(STAMP) fit.chg + +$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt + quartus_fit $(PROJECT) $(FIT_ARGS) + $(STAMP) asm.chg + $(STAMP) sta.chg + +$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt + quartus_asm $(PROJECT) $(ASM_ARGS) + +$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt + quartus_sta $(PROJECT) $(STA_ARGS) + +smart.log: $(PROJECT_FILES) + quartus_sh --determine_smart_action $(PROJECT) > smart.log + +# Project initialization +$(PROJECT_FILES): + quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" + +syn.chg: + $(STAMP) syn.chg + +fit.chg: + $(STAMP) fit.chg + +sta.chg: + $(STAMP) sta.chg + +asm.chg: + $(STAMP) asm.chg + +program: $(PROJECT).sof + quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof" + +clean: + rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox diff --git a/hw/syn/quartus/pipeline/project.sdc b/hw/syn/quartus/pipeline/project.sdc new file mode 100644 index 00000000..3c588f3b --- /dev/null +++ b/hw/syn/quartus/pipeline/project.sdc @@ -0,0 +1,9 @@ +set_time_format -unit ns -decimal_places 3 + +create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}] + +derive_pll_clocks -create_base_clocks +derive_clock_uncertainty + + + diff --git a/hw/syn/quartus/pipeline/project.tcl b/hw/syn/quartus/pipeline/project.tcl new file mode 100644 index 00000000..afe69d48 --- /dev/null +++ b/hw/syn/quartus/pipeline/project.tcl @@ -0,0 +1,41 @@ +load_package flow +package require cmdline + +set options { \ + { "project.arg" "" "Project name" } \ + { "family.arg" "" "Device family name" } \ + { "device.arg" "" "Device name" } \ + { "top.arg" "" "Top level module" } \ + { "sdc.arg" "" "Timing Design Constraints file" } \ + { "src.arg" "" "Verilog source file" } \ + { "inc.arg" "." "Include path" } \ +} + +array set opts [::cmdline::getoptions quartus(args) $options] + +project_new $opts(project) -overwrite + +set_global_assignment -name FAMILY $opts(family) +set_global_assignment -name DEVICE $opts(device) +set_global_assignment -name TOP_LEVEL_ENTITY $opts(top) +set_global_assignment -name VERILOG_FILE $opts(src) +set_global_assignment -name SEARCH_PATH $opts(inc) +set_global_assignment -name SDC_FILE $opts(sdc) +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009 + +proc make_all_pins_virtual {} { + execute_module -tool map + set name_ids [get_names -filter * -node_type pin] + foreach_in_collection name_id $name_ids { + set pin_name [get_name_info -info full_path $name_id] + post_message "Making VIRTUAL_PIN assignment to $pin_name" + set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON + } + export_assignments +} + +make_all_pins_virtual + +project_close \ No newline at end of file