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block ram read enable fix

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This commit is contained in:
Blaise Tine
2021-09-14 01:45:01 -07:00
parent 6652e2f0e9
commit 3d7baf1640
13 changed files with 32 additions and 64 deletions
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3
hw/rtl/VX_gpr_stage.v
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@@ -43,7 +43,6 @@ module VX_gpr_stage #(
.wren (wren[i]), .wren (wren[i]),
.waddr (waddr), .waddr (waddr),
.wdata (writeback_if.data[i]), .wdata (writeback_if.data[i]),
.rden (1'b1),
.raddr (raddr1), .raddr (raddr1),
.rdata (gpr_rsp_if.rs1_data[i]) .rdata (gpr_rsp_if.rs1_data[i])
); );
@@ -58,7 +57,6 @@ module VX_gpr_stage #(
.wren (wren[i]), .wren (wren[i]),
.waddr (waddr), .waddr (waddr),
.wdata (writeback_if.data[i]), .wdata (writeback_if.data[i]),
.rden (1'b1),
.raddr (raddr2), .raddr (raddr2),
.rdata (gpr_rsp_if.rs2_data[i]) .rdata (gpr_rsp_if.rs2_data[i])
); );
@@ -79,7 +77,6 @@ module VX_gpr_stage #(
.wren (wren[i]), .wren (wren[i]),
.waddr (waddr), .waddr (waddr),
.wdata (writeback_if.data[i]), .wdata (writeback_if.data[i]),
.rden (1'b1),
.raddr (raddr3), .raddr (raddr3),
.rdata (gpr_rsp_if.rs3_data[i]) .rdata (gpr_rsp_if.rs3_data[i])
); );

1
hw/rtl/VX_icache_stage.v
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@@ -41,7 +41,6 @@ module VX_icache_stage #(
.wren (icache_req_fire), .wren (icache_req_fire),
.waddr (req_tag), .waddr (req_tag),
.wdata ({ifetch_req_if.PC, ifetch_req_if.tmask}), .wdata ({ifetch_req_if.PC, ifetch_req_if.tmask}),
.rden (1'b1),
.raddr (rsp_tag), .raddr (rsp_tag),
.rdata ({rsp_PC, rsp_tmask}) .rdata ({rsp_PC, rsp_tmask})
); );

1
hw/rtl/VX_ipdom_stack.v
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@@ -46,7 +46,6 @@ module VX_ipdom_stack #(
.wren (push), .wren (push),
.waddr (wr_ptr), .waddr (wr_ptr),
.wdata ({q2, q1}), .wdata ({q2, q1}),
.rden (1'b1),
.raddr (rd_ptr), .raddr (rd_ptr),
.rdata ({d2, d1}) .rdata ({d2, d1})
); );

1
hw/rtl/cache/VX_data_access.v vendored
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@@ -117,7 +117,6 @@ module VX_data_access #(
.addr (line_addr), .addr (line_addr),
.wren (wren), .wren (wren),
.wdata (wdata), .wdata (wdata),
.rden (1'b1),
.rdata (rdata) .rdata (rdata)
); );

1
hw/rtl/cache/VX_miss_resrv.v vendored
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@@ -181,7 +181,6 @@ module VX_miss_resrv #(
.raddr (dequeue_id_r), .raddr (dequeue_id_r),
.wren (allocate_valid), .wren (allocate_valid),
.wdata (allocate_data), .wdata (allocate_data),
.rden (1'b1),
.rdata (dequeue_data) .rdata (dequeue_data)
); );

1
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -181,7 +181,6 @@ module VX_shared_mem #(
.addr (addr), .addr (addr),
.wren (wren), .wren (wren),
.wdata (per_bank_core_req_data[i]), .wdata (per_bank_core_req_data[i]),
.rden (1'b1),
.rdata (per_bank_core_rsp_data[i]) .rdata (per_bank_core_rsp_data[i])
); );
end end

7
hw/rtl/cache/VX_tag_access.v vendored
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@@ -46,15 +46,14 @@ module VX_tag_access #(
wire [`LINE_SELECT_BITS-1:0] line_addr = addr [`LINE_SELECT_BITS-1:0]; wire [`LINE_SELECT_BITS-1:0] line_addr = addr [`LINE_SELECT_BITS-1:0];
VX_sp_ram #( VX_sp_ram #(
.DATAW (`TAG_SELECT_BITS + 1), .DATAW (`TAG_SELECT_BITS + 1),
.SIZE (`LINES_PER_BANK), .SIZE (`LINES_PER_BANK),
.NO_RWCHECK (1) .NO_RWCHECK (1)
) tag_store ( ) tag_store (
.clk( clk), .clk( clk),
.addr (line_addr), .addr (line_addr),
.wren (fill), .wren (fill),
.wdata ({!is_flush, line_tag}), .wdata ({!is_flush, line_tag}),
.rden (1'b1),
.rdata ({read_valid, read_tag}) .rdata ({read_valid, read_tag})
); );

26
hw/rtl/libs/VX_dp_ram.v
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@@ -5,10 +5,10 @@ module VX_dp_ram #(
parameter DATAW = 1, parameter DATAW = 1,
parameter SIZE = 1, parameter SIZE = 1,
parameter BYTEENW = 1, parameter BYTEENW = 1,
parameter OUT_REG = 0, parameter OUT_REG = 0,
parameter NO_RWCHECK = 0, parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0, parameter LUTRAM = 0,
parameter ADDRW = $clog2(SIZE),
parameter INIT_ENABLE = 0, parameter INIT_ENABLE = 0,
parameter INIT_FILE = "", parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0 parameter [DATAW-1:0] INIT_VALUE = 0
@@ -17,7 +17,6 @@ module VX_dp_ram #(
input wire [BYTEENW-1:0] wren, input wire [BYTEENW-1:0] wren,
input wire [ADDRW-1:0] waddr, input wire [ADDRW-1:0] waddr,
input wire [DATAW-1:0] wdata, input wire [DATAW-1:0] wdata,
input wire rden,
input wire [ADDRW-1:0] raddr, input wire [ADDRW-1:0] raddr,
output wire [DATAW-1:0] rdata output wire [DATAW-1:0] rdata
); );
@@ -47,8 +46,7 @@ module VX_dp_ram #(
if (wren[i]) if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8]; ram[waddr][i] <= wdata[i * 8 +: 8];
end end
if (rden) rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end end
end else begin end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
@@ -58,13 +56,11 @@ module VX_dp_ram #(
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
ram[waddr] <= wdata; ram[waddr] <= wdata;
if (rden) rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end end
end end
assign rdata = rdata_r; assign rdata = rdata_r;
end else begin end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -103,8 +99,7 @@ module VX_dp_ram #(
if (wren[i]) if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8]; ram[waddr][i] <= wdata[i * 8 +: 8];
end end
if (rden) rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end end
end else begin end else begin
reg [DATAW-1:0] ram [SIZE-1:0]; reg [DATAW-1:0] ram [SIZE-1:0];
@@ -114,13 +109,11 @@ module VX_dp_ram #(
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
ram[waddr] <= wdata; ram[waddr] <= wdata;
if (rden) rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end end
end end
assign rdata = rdata_r; assign rdata = rdata_r;
end else begin end else begin
`UNUSED_VAR (rden)
if (NO_RWCHECK) begin if (NO_RWCHECK) begin
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -185,8 +178,7 @@ module VX_dp_ram #(
if (wren[i]) if (wren[i])
ram[waddr][i] <= wdata[i * 8 +: 8]; ram[waddr][i] <= wdata[i * 8 +: 8];
end end
if (rden) rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end end
end else begin end else begin
reg [DATAW-1:0] ram [SIZE-1:0]; reg [DATAW-1:0] ram [SIZE-1:0];
@@ -196,13 +188,11 @@ module VX_dp_ram #(
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
ram[waddr] <= wdata; ram[waddr] <= wdata;
if (rden) rdata_r <= ram[raddr];
rdata_r <= ram[raddr];
end end
end end
assign rdata = rdata_r; assign rdata = rdata_r;
end else begin end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data; reg [DATAW-1:0] prev_data;

6
hw/rtl/libs/VX_elastic_buffer.v
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@@ -2,10 +2,10 @@
`TRACING_OFF `TRACING_OFF
module VX_elastic_buffer #( module VX_elastic_buffer #(
parameter DATAW = 1, parameter DATAW = 1,
parameter SIZE = 2, parameter SIZE = 2,
parameter OUT_REG = 0, parameter OUT_REG = 0,
parameter LUTRAM = 0 parameter LUTRAM = 0
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,

18
hw/rtl/libs/VX_fifo_queue.v
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@@ -2,14 +2,14 @@
`TRACING_OFF `TRACING_OFF
module VX_fifo_queue #( module VX_fifo_queue #(
parameter DATAW = 1, parameter DATAW = 1,
parameter SIZE = 2, parameter SIZE = 2,
parameter ALM_FULL = (SIZE - 1), parameter ALM_FULL = (SIZE - 1),
parameter ALM_EMPTY = 1, parameter ALM_EMPTY = 1,
parameter ADDRW = $clog2(SIZE), parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1), parameter SIZEW = $clog2(SIZE+1),
parameter OUT_REG = 0, parameter OUT_REG = 0,
parameter LUTRAM = 1 parameter LUTRAM = 1
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -163,7 +163,6 @@ module VX_fifo_queue #(
.wren (push), .wren (push),
.waddr (wr_ptr_r), .waddr (wr_ptr_r),
.wdata (data_in), .wdata (data_in),
.rden (1'b1),
.raddr (rd_ptr_r), .raddr (rd_ptr_r),
.rdata (data_out) .rdata (data_out)
); );
@@ -206,7 +205,6 @@ module VX_fifo_queue #(
.wren (push), .wren (push),
.waddr (wr_ptr_r), .waddr (wr_ptr_r),
.wdata (data_in), .wdata (data_in),
.rden (1'b1),
.raddr (rd_ptr_n_r), .raddr (rd_ptr_n_r),
.rdata (dout) .rdata (dout)
); );

1
hw/rtl/libs/VX_index_buffer.v
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@@ -76,7 +76,6 @@ module VX_index_buffer #(
.wren (acquire_slot), .wren (acquire_slot),
.waddr (write_addr_r), .waddr (write_addr_r),
.wdata (write_data), .wdata (write_data),
.rden (1'b1),
.raddr (read_addr), .raddr (read_addr),
.rdata (read_data) .rdata (read_data)
); );

2
hw/rtl/libs/VX_skid_buffer.v
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@@ -5,7 +5,7 @@ module VX_skid_buffer #(
parameter DATAW = 1, parameter DATAW = 1,
parameter PASSTHRU = 0, parameter PASSTHRU = 0,
parameter NOBACKPRESSURE = 0, parameter NOBACKPRESSURE = 0,
parameter OUT_REG = 0 parameter OUT_REG = 0
) ( ) (
input wire clk, input wire clk,
input wire reset, input wire reset,

26
hw/rtl/libs/VX_sp_ram.v
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@@ -5,10 +5,10 @@ module VX_sp_ram #(
parameter DATAW = 1, parameter DATAW = 1,
parameter SIZE = 1, parameter SIZE = 1,
parameter BYTEENW = 1, parameter BYTEENW = 1,
parameter OUT_REG = 0, parameter OUT_REG = 0,
parameter NO_RWCHECK = 0, parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0, parameter LUTRAM = 0,
parameter ADDRW = $clog2(SIZE),
parameter INIT_ENABLE = 0, parameter INIT_ENABLE = 0,
parameter INIT_FILE = "", parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0 parameter [DATAW-1:0] INIT_VALUE = 0
@@ -17,7 +17,6 @@ module VX_sp_ram #(
input wire [ADDRW-1:0] addr, input wire [ADDRW-1:0] addr,
input wire [BYTEENW-1:0] wren, input wire [BYTEENW-1:0] wren,
input wire [DATAW-1:0] wdata, input wire [DATAW-1:0] wdata,
input wire rden,
output wire [DATAW-1:0] rdata output wire [DATAW-1:0] rdata
); );
@@ -47,8 +46,7 @@ module VX_sp_ram #(
if (wren[i]) if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8]; ram[addr][i] <= wdata[i * 8 +: 8];
end end
if (rden) rdata_r <= ram[addr];
rdata_r <= ram[addr];
end end
end else begin end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
@@ -58,13 +56,11 @@ module VX_sp_ram #(
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
ram[addr] <= wdata; ram[addr] <= wdata;
if (rden) rdata_r <= ram[addr];
rdata_r <= ram[addr];
end end
end end
assign rdata = rdata_r; assign rdata = rdata_r;
end else begin end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -103,8 +99,7 @@ module VX_sp_ram #(
if (wren[i]) if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8]; ram[addr][i] <= wdata[i * 8 +: 8];
end end
if (rden) rdata_r <= ram[addr];
rdata_r <= ram[addr];
end end
end else begin end else begin
reg [DATAW-1:0] ram [SIZE-1:0]; reg [DATAW-1:0] ram [SIZE-1:0];
@@ -114,13 +109,11 @@ module VX_sp_ram #(
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
ram[addr] <= wdata; ram[addr] <= wdata;
if (rden) rdata_r <= ram[addr];
rdata_r <= ram[addr];
end end
end end
assign rdata = rdata_r; assign rdata = rdata_r;
end else begin end else begin
`UNUSED_VAR (rden)
if (NO_RWCHECK) begin if (NO_RWCHECK) begin
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
`NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -185,8 +178,7 @@ module VX_sp_ram #(
if (wren[i]) if (wren[i])
ram[addr][i] <= wdata[i * 8 +: 8]; ram[addr][i] <= wdata[i * 8 +: 8];
end end
if (rden) rdata_r <= ram[addr];
rdata_r <= ram[addr];
end end
end else begin end else begin
reg [DATAW-1:0] ram [SIZE-1:0]; reg [DATAW-1:0] ram [SIZE-1:0];
@@ -196,13 +188,11 @@ module VX_sp_ram #(
always @(posedge clk) begin always @(posedge clk) begin
if (wren) if (wren)
ram[addr] <= wdata; ram[addr] <= wdata;
if (rden) rdata_r <= ram[addr];
rdata_r <= ram[addr];
end end
end end
assign rdata = rdata_r; assign rdata = rdata_r;
end else begin end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
reg [DATAW-1:0] prev_data; reg [DATAW-1:0] prev_data;