From 3d7baf1640ae167b1df2df22cd86a73f2ac5b13f Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 14 Sep 2021 01:45:01 -0700 Subject: [PATCH] block ram read enable fix --- hw/rtl/VX_gpr_stage.v | 3 --- hw/rtl/VX_icache_stage.v | 1 - hw/rtl/VX_ipdom_stack.v | 1 - hw/rtl/cache/VX_data_access.v | 1 - hw/rtl/cache/VX_miss_resrv.v | 1 - hw/rtl/cache/VX_shared_mem.v | 1 - hw/rtl/cache/VX_tag_access.v | 7 +++---- hw/rtl/libs/VX_dp_ram.v | 26 ++++++++------------------ hw/rtl/libs/VX_elastic_buffer.v | 6 +++--- hw/rtl/libs/VX_fifo_queue.v | 18 ++++++++---------- hw/rtl/libs/VX_index_buffer.v | 1 - hw/rtl/libs/VX_skid_buffer.v | 2 +- hw/rtl/libs/VX_sp_ram.v | 28 +++++++++------------------- 13 files changed, 32 insertions(+), 64 deletions(-) diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 7b80e084..cf601b9a 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -43,7 +43,6 @@ module VX_gpr_stage #( .wren (wren[i]), .waddr (waddr), .wdata (writeback_if.data[i]), - .rden (1'b1), .raddr (raddr1), .rdata (gpr_rsp_if.rs1_data[i]) ); @@ -58,7 +57,6 @@ module VX_gpr_stage #( .wren (wren[i]), .waddr (waddr), .wdata (writeback_if.data[i]), - .rden (1'b1), .raddr (raddr2), .rdata (gpr_rsp_if.rs2_data[i]) ); @@ -79,7 +77,6 @@ module VX_gpr_stage #( .wren (wren[i]), .waddr (waddr), .wdata (writeback_if.data[i]), - .rden (1'b1), .raddr (raddr3), .rdata (gpr_rsp_if.rs3_data[i]) ); diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 59dc1970..c17553a8 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -41,7 +41,6 @@ module VX_icache_stage #( .wren (icache_req_fire), .waddr (req_tag), .wdata ({ifetch_req_if.PC, ifetch_req_if.tmask}), - .rden (1'b1), .raddr (rsp_tag), .rdata ({rsp_PC, rsp_tmask}) ); diff --git a/hw/rtl/VX_ipdom_stack.v b/hw/rtl/VX_ipdom_stack.v index 357f7c18..4cdb1317 100644 --- a/hw/rtl/VX_ipdom_stack.v +++ b/hw/rtl/VX_ipdom_stack.v @@ -46,7 +46,6 @@ module VX_ipdom_stack #( .wren (push), .waddr (wr_ptr), .wdata ({q2, q1}), - .rden (1'b1), .raddr (rd_ptr), .rdata ({d2, d1}) ); diff --git a/hw/rtl/cache/VX_data_access.v b/hw/rtl/cache/VX_data_access.v index 8b45530e..018f3805 100644 --- a/hw/rtl/cache/VX_data_access.v +++ b/hw/rtl/cache/VX_data_access.v @@ -117,7 +117,6 @@ module VX_data_access #( .addr (line_addr), .wren (wren), .wdata (wdata), - .rden (1'b1), .rdata (rdata) ); diff --git a/hw/rtl/cache/VX_miss_resrv.v b/hw/rtl/cache/VX_miss_resrv.v index 953554b9..0f7b0819 100644 --- a/hw/rtl/cache/VX_miss_resrv.v +++ b/hw/rtl/cache/VX_miss_resrv.v @@ -181,7 +181,6 @@ module VX_miss_resrv #( .raddr (dequeue_id_r), .wren (allocate_valid), .wdata (allocate_data), - .rden (1'b1), .rdata (dequeue_data) ); diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v index 8bcdfda2..0be698f1 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.v @@ -181,7 +181,6 @@ module VX_shared_mem #( .addr (addr), .wren (wren), .wdata (per_bank_core_req_data[i]), - .rden (1'b1), .rdata (per_bank_core_rsp_data[i]) ); end diff --git a/hw/rtl/cache/VX_tag_access.v b/hw/rtl/cache/VX_tag_access.v index b0b4226a..c3a8bc80 100644 --- a/hw/rtl/cache/VX_tag_access.v +++ b/hw/rtl/cache/VX_tag_access.v @@ -46,15 +46,14 @@ module VX_tag_access #( wire [`LINE_SELECT_BITS-1:0] line_addr = addr [`LINE_SELECT_BITS-1:0]; VX_sp_ram #( - .DATAW (`TAG_SELECT_BITS + 1), - .SIZE (`LINES_PER_BANK), - .NO_RWCHECK (1) + .DATAW (`TAG_SELECT_BITS + 1), + .SIZE (`LINES_PER_BANK), + .NO_RWCHECK (1) ) tag_store ( .clk( clk), .addr (line_addr), .wren (fill), .wdata ({!is_flush, line_tag}), - .rden (1'b1), .rdata ({read_valid, read_tag}) ); diff --git a/hw/rtl/libs/VX_dp_ram.v b/hw/rtl/libs/VX_dp_ram.v index 0e14fa54..db381485 100644 --- a/hw/rtl/libs/VX_dp_ram.v +++ b/hw/rtl/libs/VX_dp_ram.v @@ -5,10 +5,10 @@ module VX_dp_ram #( parameter DATAW = 1, parameter SIZE = 1, parameter BYTEENW = 1, - parameter OUT_REG = 0, + parameter OUT_REG = 0, parameter NO_RWCHECK = 0, - parameter ADDRW = $clog2(SIZE), parameter LUTRAM = 0, + parameter ADDRW = $clog2(SIZE), parameter INIT_ENABLE = 0, parameter INIT_FILE = "", parameter [DATAW-1:0] INIT_VALUE = 0 @@ -17,7 +17,6 @@ module VX_dp_ram #( input wire [BYTEENW-1:0] wren, input wire [ADDRW-1:0] waddr, input wire [DATAW-1:0] wdata, - input wire rden, input wire [ADDRW-1:0] raddr, output wire [DATAW-1:0] rdata ); @@ -47,8 +46,7 @@ module VX_dp_ram #( if (wren[i]) ram[waddr][i] <= wdata[i * 8 +: 8]; end - if (rden) - rdata_r <= ram[raddr]; + rdata_r <= ram[raddr]; end end else begin `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; @@ -58,13 +56,11 @@ module VX_dp_ram #( always @(posedge clk) begin if (wren) ram[waddr] <= wdata; - if (rden) - rdata_r <= ram[raddr]; + rdata_r <= ram[raddr]; end end assign rdata = rdata_r; end else begin - `UNUSED_VAR (rden) if (BYTEENW > 1) begin `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; @@ -103,8 +99,7 @@ module VX_dp_ram #( if (wren[i]) ram[waddr][i] <= wdata[i * 8 +: 8]; end - if (rden) - rdata_r <= ram[raddr]; + rdata_r <= ram[raddr]; end end else begin reg [DATAW-1:0] ram [SIZE-1:0]; @@ -114,13 +109,11 @@ module VX_dp_ram #( always @(posedge clk) begin if (wren) ram[waddr] <= wdata; - if (rden) - rdata_r <= ram[raddr]; + rdata_r <= ram[raddr]; end end assign rdata = rdata_r; end else begin - `UNUSED_VAR (rden) if (NO_RWCHECK) begin if (BYTEENW > 1) begin `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; @@ -185,8 +178,7 @@ module VX_dp_ram #( if (wren[i]) ram[waddr][i] <= wdata[i * 8 +: 8]; end - if (rden) - rdata_r <= ram[raddr]; + rdata_r <= ram[raddr]; end end else begin reg [DATAW-1:0] ram [SIZE-1:0]; @@ -196,13 +188,11 @@ module VX_dp_ram #( always @(posedge clk) begin if (wren) ram[waddr] <= wdata; - if (rden) - rdata_r <= ram[raddr]; + rdata_r <= ram[raddr]; end end assign rdata = rdata_r; end else begin - `UNUSED_VAR (rden) if (BYTEENW > 1) begin reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; reg [DATAW-1:0] prev_data; diff --git a/hw/rtl/libs/VX_elastic_buffer.v b/hw/rtl/libs/VX_elastic_buffer.v index ac36fc62..4eb5dc90 100644 --- a/hw/rtl/libs/VX_elastic_buffer.v +++ b/hw/rtl/libs/VX_elastic_buffer.v @@ -2,10 +2,10 @@ `TRACING_OFF module VX_elastic_buffer #( - parameter DATAW = 1, - parameter SIZE = 2, + parameter DATAW = 1, + parameter SIZE = 2, parameter OUT_REG = 0, - parameter LUTRAM = 0 + parameter LUTRAM = 0 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/libs/VX_fifo_queue.v b/hw/rtl/libs/VX_fifo_queue.v index cc812cfc..fcff5ac9 100644 --- a/hw/rtl/libs/VX_fifo_queue.v +++ b/hw/rtl/libs/VX_fifo_queue.v @@ -2,14 +2,14 @@ `TRACING_OFF module VX_fifo_queue #( - parameter DATAW = 1, - parameter SIZE = 2, - parameter ALM_FULL = (SIZE - 1), - parameter ALM_EMPTY = 1, - parameter ADDRW = $clog2(SIZE), - parameter SIZEW = $clog2(SIZE+1), - parameter OUT_REG = 0, - parameter LUTRAM = 1 + parameter DATAW = 1, + parameter SIZE = 2, + parameter ALM_FULL = (SIZE - 1), + parameter ALM_EMPTY = 1, + parameter ADDRW = $clog2(SIZE), + parameter SIZEW = $clog2(SIZE+1), + parameter OUT_REG = 0, + parameter LUTRAM = 1 ) ( input wire clk, input wire reset, @@ -163,7 +163,6 @@ module VX_fifo_queue #( .wren (push), .waddr (wr_ptr_r), .wdata (data_in), - .rden (1'b1), .raddr (rd_ptr_r), .rdata (data_out) ); @@ -206,7 +205,6 @@ module VX_fifo_queue #( .wren (push), .waddr (wr_ptr_r), .wdata (data_in), - .rden (1'b1), .raddr (rd_ptr_n_r), .rdata (dout) ); diff --git a/hw/rtl/libs/VX_index_buffer.v b/hw/rtl/libs/VX_index_buffer.v index df6a4aef..b8fe7729 100644 --- a/hw/rtl/libs/VX_index_buffer.v +++ b/hw/rtl/libs/VX_index_buffer.v @@ -76,7 +76,6 @@ module VX_index_buffer #( .wren (acquire_slot), .waddr (write_addr_r), .wdata (write_data), - .rden (1'b1), .raddr (read_addr), .rdata (read_data) ); diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v index d295db55..b96857e3 100644 --- a/hw/rtl/libs/VX_skid_buffer.v +++ b/hw/rtl/libs/VX_skid_buffer.v @@ -5,7 +5,7 @@ module VX_skid_buffer #( parameter DATAW = 1, parameter PASSTHRU = 0, parameter NOBACKPRESSURE = 0, - parameter OUT_REG = 0 + parameter OUT_REG = 0 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/libs/VX_sp_ram.v b/hw/rtl/libs/VX_sp_ram.v index 2cf7bff0..9485e09c 100644 --- a/hw/rtl/libs/VX_sp_ram.v +++ b/hw/rtl/libs/VX_sp_ram.v @@ -5,10 +5,10 @@ module VX_sp_ram #( parameter DATAW = 1, parameter SIZE = 1, parameter BYTEENW = 1, - parameter OUT_REG = 0, + parameter OUT_REG = 0, parameter NO_RWCHECK = 0, - parameter ADDRW = $clog2(SIZE), parameter LUTRAM = 0, + parameter ADDRW = $clog2(SIZE), parameter INIT_ENABLE = 0, parameter INIT_FILE = "", parameter [DATAW-1:0] INIT_VALUE = 0 @@ -16,8 +16,7 @@ module VX_sp_ram #( input wire clk, input wire [ADDRW-1:0] addr, input wire [BYTEENW-1:0] wren, - input wire [DATAW-1:0] wdata, - input wire rden, + input wire [DATAW-1:0] wdata, output wire [DATAW-1:0] rdata ); @@ -47,8 +46,7 @@ module VX_sp_ram #( if (wren[i]) ram[addr][i] <= wdata[i * 8 +: 8]; end - if (rden) - rdata_r <= ram[addr]; + rdata_r <= ram[addr]; end end else begin `USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0]; @@ -58,13 +56,11 @@ module VX_sp_ram #( always @(posedge clk) begin if (wren) ram[addr] <= wdata; - if (rden) - rdata_r <= ram[addr]; + rdata_r <= ram[addr]; end end assign rdata = rdata_r; end else begin - `UNUSED_VAR (rden) if (BYTEENW > 1) begin `USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; @@ -103,8 +99,7 @@ module VX_sp_ram #( if (wren[i]) ram[addr][i] <= wdata[i * 8 +: 8]; end - if (rden) - rdata_r <= ram[addr]; + rdata_r <= ram[addr]; end end else begin reg [DATAW-1:0] ram [SIZE-1:0]; @@ -114,13 +109,11 @@ module VX_sp_ram #( always @(posedge clk) begin if (wren) ram[addr] <= wdata; - if (rden) - rdata_r <= ram[addr]; + rdata_r <= ram[addr]; end end assign rdata = rdata_r; end else begin - `UNUSED_VAR (rden) if (NO_RWCHECK) begin if (BYTEENW > 1) begin `NO_RW_RAM_CHECK reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; @@ -185,8 +178,7 @@ module VX_sp_ram #( if (wren[i]) ram[addr][i] <= wdata[i * 8 +: 8]; end - if (rden) - rdata_r <= ram[addr]; + rdata_r <= ram[addr]; end end else begin reg [DATAW-1:0] ram [SIZE-1:0]; @@ -196,13 +188,11 @@ module VX_sp_ram #( always @(posedge clk) begin if (wren) ram[addr] <= wdata; - if (rden) - rdata_r <= ram[addr]; + rdata_r <= ram[addr]; end end assign rdata = rdata_r; end else begin - `UNUSED_VAR (rden) if (BYTEENW > 1) begin reg [BYTEENW-1:0][7:0] ram [SIZE-1:0]; reg [DATAW-1:0] prev_data;