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block ram read enable fix

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This commit is contained in:
Blaise Tine
2021-09-14 01:45:01 -07:00
parent 6652e2f0e9
commit 3d7baf1640
13 changed files with 32 additions and 64 deletions
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1
hw/rtl/cache/VX_data_access.v vendored
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@@ -117,7 +117,6 @@ module VX_data_access #(
.addr (line_addr),
.wren (wren),
.wdata (wdata),
.rden (1'b1),
.rdata (rdata)
);

1
hw/rtl/cache/VX_miss_resrv.v vendored
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@@ -181,7 +181,6 @@ module VX_miss_resrv #(
.raddr (dequeue_id_r),
.wren (allocate_valid),
.wdata (allocate_data),
.rden (1'b1),
.rdata (dequeue_data)
);

1
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -181,7 +181,6 @@ module VX_shared_mem #(
.addr (addr),
.wren (wren),
.wdata (per_bank_core_req_data[i]),
.rden (1'b1),
.rdata (per_bank_core_rsp_data[i])
);
end

7
hw/rtl/cache/VX_tag_access.v vendored
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@@ -46,15 +46,14 @@ module VX_tag_access #(
wire [`LINE_SELECT_BITS-1:0] line_addr = addr [`LINE_SELECT_BITS-1:0];
VX_sp_ram #(
.DATAW (`TAG_SELECT_BITS + 1),
.SIZE (`LINES_PER_BANK),
.NO_RWCHECK (1)
.DATAW (`TAG_SELECT_BITS + 1),
.SIZE (`LINES_PER_BANK),
.NO_RWCHECK (1)
) tag_store (
.clk( clk),
.addr (line_addr),
.wren (fill),
.wdata ({!is_flush, line_tag}),
.rden (1'b1),
.rdata ({read_valid, read_tag})
);