opae build fix

hw/rtl/VX_csr_handler.v

@@ -1,69 +0,0 @@
-module VX_csr_handler (
-	input wire        clk,
-	input wire[`CSR_ADDR_SIZE-1:0] in_decode_csr_address, // done
-	VX_csr_write_request_if csr_w_req_if,
-	input wire        in_wb_valid,
-	output wire[31:0] out_decode_csr_data // done
-);
-	wire       in_mem_is_csr;
-	wire[`CSR_ADDR_SIZE-1:0] in_mem_csr_address;
-	wire[31:0] in_mem_csr_result;
-
-	assign in_mem_is_csr      = csr_w_req_if.is_csr;
-	assign in_mem_csr_address = csr_w_req_if.csr_address;
-	assign in_mem_csr_result  = csr_w_req_if.csr_result;
-
-	reg [`CSR_WIDTH-1:0] csr [`NUM_CSRS-1:0];
-	
-	reg [63:0] cycle;
-	reg [63:0] instret;	
-	reg [`CSR_ADDR_SIZE-1:0] decode_csr_address;
-
-	wire read_cycle;
-	wire read_cycleh;
-	wire read_instret;
-	wire read_instreth;
-
-	initial begin
-		cycle              = 0;
-		instret            = 0;
-		decode_csr_address = 0;
-	end
-
-	always @(posedge clk) begin
-		cycle              <= cycle   + 1;
-		decode_csr_address <= in_decode_csr_address;
-		if (in_wb_valid) begin
-			instret <= instret + 1;
-		end
-	end
-
-	reg[`CSR_WIDTH-1:0] data_read;
-
-	always @(posedge clk) begin
-		if (in_mem_is_csr) begin
-			csr[in_mem_csr_address] <= in_mem_csr_result[11:0];
-		end
-	end
-
-	assign data_read = csr[decode_csr_address];
-
-	assign read_cycle    = decode_csr_address == `CSR_CYCL_L;
-	assign read_cycleh   = decode_csr_address == `CSR_CYCL_H;
-	assign read_instret  = decode_csr_address == `CSR_INST_L;
-	assign read_instreth = decode_csr_address == `CSR_INST_H;
-
-	assign out_decode_csr_data = read_cycle    ? cycle[31:0] :
-						  		 read_cycleh   ? cycle[63:32] : 
-								 read_instret  ? instret[31:0] :
-								 read_instreth ? instret[63:32] : 
-								 				 {{20{1'b0}}, data_read};
-
-endmodule // VX_csr_handler
-
-
-
-
-
-
-

hw/rtl/VX_define.v

@@ -4,29 +4,10 @@
 `include "./VX_config.v"
 
 // `define QUEUE_FORCE_MLAB 1
-
 // `define SYN 1
 // `define ASIC 1
 // `define SYN_FUNC 1
 
-`define DEBUG_BEGIN /* verilator lint_off UNUSED */ 
-`define DEBUG_END   /* verilator lint_on UNUSED */     
-
-`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \
-                              /* verilator lint_off PINCONNECTEMPTY */ \
-                              /* verilator lint_off DECLFILENAME */
-
-`define IGNORE_WARNINGS_END   /* verilator lint_on UNUSED */ \
-                              /* verilator lint_on PINCONNECTEMPTY */ \
-                              /* verilator lint_on DECLFILENAME */
-
-`define STRINGIFY(x) `"x`"
-
-`define STATIC_ASSERT(cond, msg)    \
-    generate                        \
-        if (!(cond)) $error(msg);   \
-    endgenerate
-
 `define LOG2UP(x) ((x > 1) ? $clog2(x) : 1)
 
 `define NUM_CORES_PER_CLUSTER (`NUM_CORES / `NUM_CLUSTERS)
@@ -196,5 +177,25 @@
 // Bank Number of words in a line
 `define L3BANK_LINE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES)
 
+//=============================================================================
+
+`define DEBUG_BEGIN /* verilator lint_off UNUSED */ 
+`define DEBUG_END   /* verilator lint_on UNUSED */     
+
+`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \
+                              /* verilator lint_off PINCONNECTEMPTY */ \
+                              /* verilator lint_off DECLFILENAME */
+
+`define IGNORE_WARNINGS_END   /* verilator lint_on UNUSED */ \
+                              /* verilator lint_on PINCONNECTEMPTY */ \
+                              /* verilator lint_on DECLFILENAME */
+
+`define STRINGIFY(x) `"x`"
+
+`define STATIC_ASSERT(cond, msg)    \
+    generate                        \
+        if (!(cond)) $error(msg);   \
+    endgenerate
+
  // VX_DEFINE
 `endif

hw/rtl/libs/VX_divide.v

@@ -1,3 +1,5 @@
+`include "VX_define.v"
+
 module VX_divide #(
     parameter WIDTHN=1,
     parameter WIDTHD=1,

hw/rtl/libs/VX_generic_queue.v

@@ -1,3 +1,5 @@
+`include "VX_define.v"
+
 module VX_generic_queue #(
     parameter DATAW,
     parameter SIZE = 16

hw/rtl/libs/VX_generic_register.v

@@ -1,3 +1,5 @@
+`include "VX_define.v"
+
 module VX_generic_register #( 
 	parameter N, 
 	parameter PassThru = 0

hw/rtl/libs/VX_mult.v

@@ -1,3 +1,5 @@
+`include "VX_define.v"
+
 module VX_mult #(
     parameter WIDTHA=1,
     parameter WIDTHB=1,