From 3cbecfcef075f3b82e0ce2a8f2648f50ef2452a2 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 20 Apr 2020 12:32:01 -0700 Subject: [PATCH] opae build fix --- hw/opae/sources.txt | 74 +++++++++++++++---------------- hw/rtl/VX_csr_handler.v | 69 ---------------------------- hw/rtl/VX_define.v | 39 ++++++++-------- hw/rtl/libs/VX_divide.v | 2 + hw/rtl/libs/VX_generic_queue.v | 2 + hw/rtl/libs/VX_generic_register.v | 2 + hw/rtl/libs/VX_mult.v | 2 + 7 files changed, 65 insertions(+), 125 deletions(-) delete mode 100644 hw/rtl/VX_csr_handler.v diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index 8b588a6a..9e605713 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -13,34 +13,6 @@ vortex_afu.json ../rtl/VX_config.v ../rtl/VX_define.v ../rtl/cache/VX_cache_config.vh -../rtl/Vortex_Socket.v -../rtl/Vortex_Cluster.v -../rtl/Vortex.v -../rtl/VX_front_end.v -../rtl/VX_back_end.v -../rtl/VX_fetch.v -../rtl/VX_scheduler.v -../rtl/VX_execute_unit.v -../rtl/VX_warp.v -../rtl/VX_icache_stage.v -../rtl/VX_gpr_wrapper.v -../rtl/byte_enabled_simple_dual_port_ram.v -../rtl/VX_gpgpu_inst.v -../rtl/VX_writeback.v -../rtl/VX_countones.v -../rtl/VX_csr_handler.v -../rtl/VX_csr_pipe.v -../rtl/VX_warp_scheduler.v -../rtl/VX_gpr.v -../rtl/VX_gpr_stage.v -../rtl/VX_dmem_controller.v -../rtl/VX_alu.v -../rtl/VX_csr_data.v -../rtl/VX_lsu.v -../rtl/VX_decode.v -../rtl/VX_inst_multiplex.v -../rtl/VX_csr_wrapper.v -../rtl/VX_lsu_addr_gen.v ../rtl/interfaces/VX_exec_unit_req_if.v ../rtl/interfaces/VX_branch_response_if.v @@ -74,6 +46,43 @@ vortex_afu.json ../rtl/interfaces/VX_gpu_dcache_dram_rsp_if.v ../rtl/interfaces/VX_inst_mem_wb_if.v +../rtl/libs/VX_priority_encoder_w_mask.v +../rtl/libs/VX_generic_register.v +../rtl/libs/VX_mult.v +../rtl/libs/VX_divide.v +../rtl/libs/VX_generic_stack.v +../rtl/libs/VX_generic_priority_encoder.v +../rtl/libs/VX_priority_encoder.v +../rtl/libs/VX_generic_queue.v + +../rtl/Vortex_Socket.v +../rtl/Vortex_Cluster.v +../rtl/Vortex.v +../rtl/VX_front_end.v +../rtl/VX_back_end.v +../rtl/VX_fetch.v +../rtl/VX_scheduler.v +../rtl/VX_execute_unit.v +../rtl/VX_warp.v +../rtl/VX_icache_stage.v +../rtl/VX_gpr_wrapper.v +../rtl/byte_enabled_simple_dual_port_ram.v +../rtl/VX_gpgpu_inst.v +../rtl/VX_writeback.v +../rtl/VX_countones.v +../rtl/VX_csr_pipe.v +../rtl/VX_warp_scheduler.v +../rtl/VX_gpr.v +../rtl/VX_gpr_stage.v +../rtl/VX_dmem_controller.v +../rtl/VX_alu.v +../rtl/VX_csr_data.v +../rtl/VX_lsu.v +../rtl/VX_decode.v +../rtl/VX_inst_multiplex.v +../rtl/VX_csr_wrapper.v +../rtl/VX_lsu_addr_gen.v + ../rtl/pipe_regs/VX_f_d_reg.v ../rtl/pipe_regs/VX_i_d_reg.v ../rtl/pipe_regs/VX_d_e_reg.v @@ -94,15 +103,6 @@ vortex_afu.json ../rtl/cache/VX_tag_data_structure.v ../rtl/cache/VX_prefetcher.v -../rtl/libs/VX_priority_encoder_w_mask.v -../rtl/libs/VX_generic_register.v -../rtl/libs/VX_mult.v -../rtl/libs/VX_divide.v -../rtl/libs/VX_generic_stack.v -../rtl/libs/VX_generic_priority_encoder.v -../rtl/libs/VX_priority_encoder.v -../rtl/libs/VX_generic_queue.v - ccip_interface_reg.sv ccip_std_afu.sv vortex_afu.sv \ No newline at end of file diff --git a/hw/rtl/VX_csr_handler.v b/hw/rtl/VX_csr_handler.v deleted file mode 100644 index eac1e0b9..00000000 --- a/hw/rtl/VX_csr_handler.v +++ /dev/null @@ -1,69 +0,0 @@ -module VX_csr_handler ( - input wire clk, - input wire[`CSR_ADDR_SIZE-1:0] in_decode_csr_address, // done - VX_csr_write_request_if csr_w_req_if, - input wire in_wb_valid, - output wire[31:0] out_decode_csr_data // done -); - wire in_mem_is_csr; - wire[`CSR_ADDR_SIZE-1:0] in_mem_csr_address; - wire[31:0] in_mem_csr_result; - - assign in_mem_is_csr = csr_w_req_if.is_csr; - assign in_mem_csr_address = csr_w_req_if.csr_address; - assign in_mem_csr_result = csr_w_req_if.csr_result; - - reg [`CSR_WIDTH-1:0] csr [`NUM_CSRS-1:0]; - - reg [63:0] cycle; - reg [63:0] instret; - reg [`CSR_ADDR_SIZE-1:0] decode_csr_address; - - wire read_cycle; - wire read_cycleh; - wire read_instret; - wire read_instreth; - - initial begin - cycle = 0; - instret = 0; - decode_csr_address = 0; - end - - always @(posedge clk) begin - cycle <= cycle + 1; - decode_csr_address <= in_decode_csr_address; - if (in_wb_valid) begin - instret <= instret + 1; - end - end - - reg[`CSR_WIDTH-1:0] data_read; - - always @(posedge clk) begin - if (in_mem_is_csr) begin - csr[in_mem_csr_address] <= in_mem_csr_result[11:0]; - end - end - - assign data_read = csr[decode_csr_address]; - - assign read_cycle = decode_csr_address == `CSR_CYCL_L; - assign read_cycleh = decode_csr_address == `CSR_CYCL_H; - assign read_instret = decode_csr_address == `CSR_INST_L; - assign read_instreth = decode_csr_address == `CSR_INST_H; - - assign out_decode_csr_data = read_cycle ? cycle[31:0] : - read_cycleh ? cycle[63:32] : - read_instret ? instret[31:0] : - read_instreth ? instret[63:32] : - {{20{1'b0}}, data_read}; - -endmodule // VX_csr_handler - - - - - - - diff --git a/hw/rtl/VX_define.v b/hw/rtl/VX_define.v index 60f56a43..e925fdf5 100644 --- a/hw/rtl/VX_define.v +++ b/hw/rtl/VX_define.v @@ -4,29 +4,10 @@ `include "./VX_config.v" // `define QUEUE_FORCE_MLAB 1 - // `define SYN 1 // `define ASIC 1 // `define SYN_FUNC 1 -`define DEBUG_BEGIN /* verilator lint_off UNUSED */ -`define DEBUG_END /* verilator lint_on UNUSED */ - -`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \ - /* verilator lint_off PINCONNECTEMPTY */ \ - /* verilator lint_off DECLFILENAME */ - -`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \ - /* verilator lint_on PINCONNECTEMPTY */ \ - /* verilator lint_on DECLFILENAME */ - -`define STRINGIFY(x) `"x`" - -`define STATIC_ASSERT(cond, msg) \ - generate \ - if (!(cond)) $error(msg); \ - endgenerate - `define LOG2UP(x) ((x > 1) ? $clog2(x) : 1) `define NUM_CORES_PER_CLUSTER (`NUM_CORES / `NUM_CLUSTERS) @@ -196,5 +177,25 @@ // Bank Number of words in a line `define L3BANK_LINE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES) +//============================================================================= + +`define DEBUG_BEGIN /* verilator lint_off UNUSED */ +`define DEBUG_END /* verilator lint_on UNUSED */ + +`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \ + /* verilator lint_off PINCONNECTEMPTY */ \ + /* verilator lint_off DECLFILENAME */ + +`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \ + /* verilator lint_on PINCONNECTEMPTY */ \ + /* verilator lint_on DECLFILENAME */ + +`define STRINGIFY(x) `"x`" + +`define STATIC_ASSERT(cond, msg) \ + generate \ + if (!(cond)) $error(msg); \ + endgenerate + // VX_DEFINE `endif diff --git a/hw/rtl/libs/VX_divide.v b/hw/rtl/libs/VX_divide.v index 9ce4af98..5c0964be 100644 --- a/hw/rtl/libs/VX_divide.v +++ b/hw/rtl/libs/VX_divide.v @@ -1,3 +1,5 @@ +`include "VX_define.v" + module VX_divide #( parameter WIDTHN=1, parameter WIDTHD=1, diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_generic_queue.v index f8391c3d..88cd6118 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_generic_queue.v @@ -1,3 +1,5 @@ +`include "VX_define.v" + module VX_generic_queue #( parameter DATAW, parameter SIZE = 16 diff --git a/hw/rtl/libs/VX_generic_register.v b/hw/rtl/libs/VX_generic_register.v index 4798c01f..6cfde913 100644 --- a/hw/rtl/libs/VX_generic_register.v +++ b/hw/rtl/libs/VX_generic_register.v @@ -1,3 +1,5 @@ +`include "VX_define.v" + module VX_generic_register #( parameter N, parameter PassThru = 0 diff --git a/hw/rtl/libs/VX_mult.v b/hw/rtl/libs/VX_mult.v index b6004141..2628cc15 100644 --- a/hw/rtl/libs/VX_mult.v +++ b/hw/rtl/libs/VX_mult.v @@ -1,3 +1,5 @@ +`include "VX_define.v" + module VX_mult #( parameter WIDTHA=1, parameter WIDTHB=1,