Created Images directory and updated Vortex.md with Codebase and Microarchitecture hyperlinks
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@@ -32,7 +32,7 @@ Vortex uses the SIMT (Single Instruction, Multiple Threads) execution model with
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### Vortex Pipeline/Datapath
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Vortex has a 5-stage pipeline: FI | ID | Issue | EX | WB.
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@@ -2,10 +2,11 @@
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### Table of Contents
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- Vortex Microarchitecture
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- [Vortex Codebase Layout](https://github.com/vortexgpgpu/vortex-dev/blob/master/doc/Codebase.md)
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- [Vortex Microarchitecture and Extended RISC-V ISA](https://github.com/vortexgpgpu/vortex-dev/blob/master/doc/Microarchitecture.md)
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- Vortex Software
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- [Vortex Simulation](https://github.com/vortexgpgpu/vortex-dev/blob/master/doc/Simulation.md)
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- [FPGA](https://github.com/vortexgpgpu/vortex-dev/blob/master/doc/Flubber_FPGA_Startup_Guide.md)
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- [FPGA Configuration, Program and Test](https://github.com/vortexgpgpu/vortex-dev/blob/master/doc/Flubber_FPGA_Startup_Guide.md)
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- Debugging
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- Useful Links
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