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fixed interface modports

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This commit is contained in:
Blaise Tine
2021-09-28 02:42:04 -07:00
parent 132260d84c
commit 18c1dc2f0e
7 changed files with 86 additions and 46 deletions
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6
hw/rtl/VX_pipeline.v
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@@ -22,19 +22,19 @@ module VX_pipeline #(
input wire dcache_rsp_valid,
input wire [`NUM_THREADS-1:0] dcache_rsp_tmask,
input wire [`NUM_THREADS-1:0][31:0] dcache_rsp_data,
input wire [`DCACHE_CORE_TAG_WIDTH-1:0] dcache_rsp_tag,
input wire [`DCACHE_CORE_TAG_WIDTH-1:0] dcache_rsp_tag,
output wire dcache_rsp_ready,
// Icache core request
output wire icache_req_valid,
output wire [29:0] icache_req_addr,
output wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_req_tag,
output wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_req_tag,
input wire icache_req_ready,
// Icache core response
input wire icache_rsp_valid,
input wire [31:0] icache_rsp_data,
input wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_rsp_tag,
input wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_rsp_tag,
output wire icache_rsp_ready,
`ifdef PERF_ENABLE