From 18c1dc2f0e8c941903f549ce997df99f9477a8d7 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 28 Sep 2021 02:42:04 -0700 Subject: [PATCH] fixed interface modports --- ci/regression.sh | 3 -- hw/rtl/VX_issue.v | 79 ++++++++++++++++++----------- hw/rtl/VX_pipeline.v | 6 +-- hw/rtl/VX_scoreboard.v | 16 +++--- hw/rtl/cache/VX_shared_mem.v | 5 +- hw/rtl/interfaces/VX_ibuffer_if.v | 14 +++++ hw/rtl/interfaces/VX_writeback_if.v | 9 ++++ 7 files changed, 86 insertions(+), 46 deletions(-) diff --git a/ci/regression.sh b/ci/regression.sh index 4b825960..8a5bff96 100755 --- a/ci/regression.sh +++ b/ci/regression.sh @@ -3,9 +3,6 @@ # exit when any command fails set -e -# build sources -make -s - coverage() { echo "begin coverage tests..." diff --git a/hw/rtl/VX_issue.v b/hw/rtl/VX_issue.v index 31483b9a..e6312fd4 100644 --- a/hw/rtl/VX_issue.v +++ b/hw/rtl/VX_issue.v @@ -24,11 +24,51 @@ module VX_issue #( VX_gpu_req_if.master gpu_req_if ); VX_ibuffer_if ibuffer_if(); - VX_ibuffer_if execute_if(); - VX_gpr_req_if gpr_req_if(); VX_gpr_rsp_if gpr_rsp_if(); - wire scoreboard_delay; + VX_gpr_req_if gpr_req_if(); + assign gpr_req_if.wid = ibuffer_if.wid; + assign gpr_req_if.rs1 = ibuffer_if.rs1; + assign gpr_req_if.rs2 = ibuffer_if.rs2; + assign gpr_req_if.rs3 = ibuffer_if.rs3; + + VX_writeback_if sboard_wb_if(); + assign sboard_wb_if.valid = writeback_if.valid; + assign sboard_wb_if.wid = writeback_if.wid; + assign sboard_wb_if.PC = writeback_if.PC; + assign sboard_wb_if.rd = writeback_if.rd; + assign sboard_wb_if.eop = writeback_if.eop; + assign sboard_wb_if.ready = writeback_if.ready; + + VX_ibuffer_if sboard_ib_if(); + assign sboard_ib_if.valid = ibuffer_if.valid && idmux_ib_if.ready; + assign sboard_ib_if.wid = ibuffer_if.wid; + assign sboard_ib_if.PC = ibuffer_if.PC; + assign sboard_ib_if.wb = ibuffer_if.wb; + assign sboard_ib_if.rd = ibuffer_if.rd; + assign sboard_ib_if.rd_n = ibuffer_if.rd_n; + assign sboard_ib_if.rs1_n = ibuffer_if.rs1_n; + assign sboard_ib_if.rs2_n = ibuffer_if.rs2_n; + assign sboard_ib_if.rs3_n = ibuffer_if.rs3_n; + assign sboard_ib_if.wid_n = ibuffer_if.wid_n; + + VX_ibuffer_if idmux_ib_if(); + assign idmux_ib_if.valid = ibuffer_if.valid && sboard_ib_if.ready; + assign idmux_ib_if.wid = ibuffer_if.wid; + assign idmux_ib_if.tmask = ibuffer_if.tmask; + assign idmux_ib_if.PC = ibuffer_if.PC; + assign idmux_ib_if.ex_type = ibuffer_if.ex_type; + assign idmux_ib_if.op_type = ibuffer_if.op_type; + assign idmux_ib_if.op_mod = ibuffer_if.op_mod; + assign idmux_ib_if.wb = ibuffer_if.wb; + assign idmux_ib_if.rd = ibuffer_if.rd; + assign idmux_ib_if.rs1 = ibuffer_if.rs1; + assign idmux_ib_if.imm = ibuffer_if.imm; + assign idmux_ib_if.use_PC = ibuffer_if.use_PC; + assign idmux_ib_if.use_imm = ibuffer_if.use_imm; + + // issue the instruction + assign ibuffer_if.ready = sboard_ib_if.ready && idmux_ib_if.ready; `RESET_RELAY (ibuf_reset); `RESET_RELAY (gpr_reset); @@ -48,15 +88,9 @@ module VX_issue #( ) scoreboard ( .clk (clk), .reset (reset), - .ibuffer_if (ibuffer_if), - .writeback_if(writeback_if), - .delay (scoreboard_delay) + .ibuffer_if (sboard_ib_if), + .writeback_if(sboard_wb_if) ); - - assign gpr_req_if.wid = ibuffer_if.wid; - assign gpr_req_if.rs1 = ibuffer_if.rs1; - assign gpr_req_if.rs2 = ibuffer_if.rs2; - assign gpr_req_if.rs3 = ibuffer_if.rs3; VX_gpr_stage #( .CORE_ID(CORE_ID) @@ -68,24 +102,10 @@ module VX_issue #( .gpr_rsp_if (gpr_rsp_if) ); - assign execute_if.valid = ibuffer_if.valid && ~scoreboard_delay; - assign execute_if.wid = ibuffer_if.wid; - assign execute_if.tmask = ibuffer_if.tmask; - assign execute_if.PC = ibuffer_if.PC; - assign execute_if.ex_type = ibuffer_if.ex_type; - assign execute_if.op_type = ibuffer_if.op_type; - assign execute_if.op_mod = ibuffer_if.op_mod; - assign execute_if.wb = ibuffer_if.wb; - assign execute_if.rd = ibuffer_if.rd; - assign execute_if.rs1 = ibuffer_if.rs1; - assign execute_if.imm = ibuffer_if.imm; - assign execute_if.use_PC = ibuffer_if.use_PC; - assign execute_if.use_imm = ibuffer_if.use_imm; - VX_instr_demux instr_demux ( .clk (clk), .reset (demux_reset), - .ibuffer_if (execute_if), + .ibuffer_if (idmux_ib_if), .gpr_rsp_if (gpr_rsp_if), .alu_req_if (alu_req_if), .lsu_req_if (lsu_req_if), @@ -94,10 +114,7 @@ module VX_issue #( .fpu_req_if (fpu_req_if), `endif .gpu_req_if (gpu_req_if) - ); - - // issue the instruction - assign ibuffer_if.ready = !scoreboard_delay && execute_if.ready; + ); `SCOPE_ASSIGN (issue_fire, ibuffer_if.valid && ibuffer_if.ready); `SCOPE_ASSIGN (issue_wid, ibuffer_if.wid); @@ -115,7 +132,7 @@ module VX_issue #( `SCOPE_ASSIGN (issue_use_pc, ibuffer_if.use_PC); `SCOPE_ASSIGN (issue_use_imm, ibuffer_if.use_imm); `SCOPE_ASSIGN (scoreboard_delay, scoreboard_delay); - `SCOPE_ASSIGN (execute_delay, ~execute_if.ready); + `SCOPE_ASSIGN (execute_delay, ~idmux_ib_if.ready); `SCOPE_ASSIGN (gpr_rsp_a, gpr_rsp_if.rs1_data); `SCOPE_ASSIGN (gpr_rsp_b, gpr_rsp_if.rs2_data); `SCOPE_ASSIGN (gpr_rsp_c, gpr_rsp_if.rs3_data); diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index ea763315..8bbc7ead 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -22,19 +22,19 @@ module VX_pipeline #( input wire dcache_rsp_valid, input wire [`NUM_THREADS-1:0] dcache_rsp_tmask, input wire [`NUM_THREADS-1:0][31:0] dcache_rsp_data, - input wire [`DCACHE_CORE_TAG_WIDTH-1:0] dcache_rsp_tag, + input wire [`DCACHE_CORE_TAG_WIDTH-1:0] dcache_rsp_tag, output wire dcache_rsp_ready, // Icache core request output wire icache_req_valid, output wire [29:0] icache_req_addr, - output wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_req_tag, + output wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_req_tag, input wire icache_req_ready, // Icache core response input wire icache_rsp_valid, input wire [31:0] icache_rsp_data, - input wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_rsp_tag, + input wire [`ICACHE_CORE_TAG_WIDTH-1:0] icache_rsp_tag, output wire icache_rsp_ready, `ifdef PERF_ENABLE diff --git a/hw/rtl/VX_scoreboard.v b/hw/rtl/VX_scoreboard.v index f6592c4f..9503ecdf 100644 --- a/hw/rtl/VX_scoreboard.v +++ b/hw/rtl/VX_scoreboard.v @@ -3,12 +3,11 @@ module VX_scoreboard #( parameter CORE_ID = 0 ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, - VX_ibuffer_if.slave ibuffer_if, - VX_writeback_if.slave writeback_if, - output wire delay + VX_ibuffer_if.scoreboard ibuffer_if, + VX_writeback_if.scoreboard writeback_if ); reg [`NUM_WARPS-1:0][`NUM_REGS-1:0] inuse_regs, inuse_regs_n; @@ -43,7 +42,12 @@ module VX_scoreboard #( deq_inuse_rs3 <= inuse_regs_n[ibuffer_if.wid_n][ibuffer_if.rs3_n]; end - assign delay = deq_inuse_rd | deq_inuse_rs1 | deq_inuse_rs2 | deq_inuse_rs3; + assign writeback_if.ready = 1'b1; + + assign ibuffer_if.ready = ~(deq_inuse_rd + | deq_inuse_rs1 + | deq_inuse_rs2 + | deq_inuse_rs3); `UNUSED_VAR (writeback_if.PC) diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v index 2a8f7c47..51c60a38 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.v @@ -157,7 +157,8 @@ module VX_shared_mem #( .valid_out (creq_out_valid) ); - wire crsq_last_read; + wire crsq_in_valid, crsq_in_ready; + wire crsq_last_read; assign creq_out_ready = core_req_writeonly || (crsq_in_ready && crsq_last_read); @@ -195,8 +196,6 @@ module VX_shared_mem #( wire [CORE_TAG_WIDTH-1:0] core_rsp_tag_in; reg [NUM_BANKS-1:0] bank_rsp_sel_r, bank_rsp_sel_n; - wire crsq_in_valid, crsq_in_ready; - wire crsq_in_fire = crsq_in_valid && crsq_in_ready; assign crsq_last_read = (bank_rsp_sel_n == core_req_read_mask); diff --git a/hw/rtl/interfaces/VX_ibuffer_if.v b/hw/rtl/interfaces/VX_ibuffer_if.v index bb791737..45569371 100644 --- a/hw/rtl/interfaces/VX_ibuffer_if.v +++ b/hw/rtl/interfaces/VX_ibuffer_if.v @@ -76,6 +76,20 @@ interface VX_ibuffer_if (); input wid_n, output ready ); + + modport scoreboard ( + input valid, + input wid, + input PC, + input wb, + input rd, + input rd_n, + input rs1_n, + input rs2_n, + input rs3_n, + input wid_n, + output ready + ); endinterface diff --git a/hw/rtl/interfaces/VX_writeback_if.v b/hw/rtl/interfaces/VX_writeback_if.v index 8f05fc7a..b3e2060d 100644 --- a/hw/rtl/interfaces/VX_writeback_if.v +++ b/hw/rtl/interfaces/VX_writeback_if.v @@ -36,6 +36,15 @@ interface VX_writeback_if (); output ready ); + modport scoreboard ( + input valid, + input wid, + input PC, + input rd, + input eop, + output ready + ); + endinterface `endif