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Merge branch 'rtl' of https://github.com/hansungk/vortex-private into rtl

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This commit is contained in:
Richard Yan
2024-06-12 02:17:01 -07:00
parent 7947df8a6c 5218292b6f
commit 1833e8a176
2 changed files with 86 additions and 76 deletions
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20
hw/rtl/VX_core_wrapper.sv
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@@ -495,15 +495,20 @@ module Vortex import VX_gpu_pkg::*; #(
// .busy(busy) // .busy(busy)
// ); // );
always @(*) begin always @(posedge clock) begin
if (busy === 1'b0) begin if (!reset) begin
$display("---------------- no more active warps ----------------"); if (finished) begin
`ifdef SIMULATION `ifdef SIMULATION
if ($time >= 60000) begin $display("---------------- core%2d has no more active warps ----------------", CORE_ID);
$display("simulation has probably ended. exiting"); $display("simulation has ended. exiting");
@(posedge clock) $finish(); $finish();
end
`endif `endif
// `ifdef SIMULATION
// if ($time >= 60000) begin
// $display("simulation has probably ended. exiting");
// @(posedge clock) $finish();
// end
// `endif
// TODO: lane assumed to be 4 // TODO: lane assumed to be 4
// `ifndef SYNTHESIS // `ifndef SYNTHESIS
// for (integer j = 0; j < `NUM_WARPS; j++) begin // for (integer j = 0; j < `NUM_WARPS; j++) begin
@@ -519,6 +524,7 @@ module Vortex import VX_gpu_pkg::*; #(
// @(posedge clock) $finish(); // @(posedge clock) $finish();
end end
end end
end
endmodule : Vortex endmodule : Vortex

8
hw/rtl/libs/VX_mem_scheduler.sv
View File

@@ -532,7 +532,8 @@ module VX_mem_scheduler #(
`ifndef NDEBUG `ifndef NDEBUG
wire [NUM_BANKS-1:0] mem_req_fire_s = mem_req_valid_s & mem_req_ready_s; wire [NUM_BANKS-1:0] mem_req_fire_s = mem_req_valid_s & mem_req_ready_s;
always @(posedge clk) begin always @(negedge clk) begin
if (!reset) begin
if (req_valid && req_ready) begin if (req_valid && req_ready) begin
if (req_rw) begin if (req_rw) begin
`TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask)); `TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));
@@ -572,8 +573,10 @@ module VX_mem_scheduler #(
`TRACE(1, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_raddr, rsp_batch_idx, mem_rsp_dbg_uuid)); `TRACE(1, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_raddr, rsp_batch_idx, mem_rsp_dbg_uuid));
end end
end end
end
`else `else
always @(posedge clk) begin always @(negedge clk) begin
if (!reset) begin
if (req_valid && req_ready) begin if (req_valid && req_ready) begin
if (req_rw) begin if (req_rw) begin
`TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask)); `TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));
@@ -594,6 +597,7 @@ module VX_mem_scheduler #(
`TRACE(1, (", tag=0x%0h, tag_only=0x%0h\n", rsp_tag, rsp_tag[TAG_ONLY_WIDTH-1:0])); `TRACE(1, (", tag=0x%0h, tag_only=0x%0h\n", rsp_tag, rsp_tag[TAG_ONLY_WIDTH-1:0]));
end end
end end
end
`endif `endif
endmodule endmodule