605 lines
23 KiB
Systemverilog
605 lines
23 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_mem_scheduler #(
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parameter `STRING INST_ID = "",
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parameter NUM_REQS = 1,
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parameter NUM_BANKS = 1,
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parameter ADDR_WIDTH = 32,
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parameter DATA_WIDTH = 32,
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parameter TAG_WIDTH = 8,
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parameter MEM_TAG_ID = 0, // upper section of the tag sent to the memory interface
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parameter UUID_WIDTH = 0, // upper section of the mem_tag_id containing the UUID
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parameter QUEUE_SIZE = 8,
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parameter RSP_PARTIAL = 0,
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parameter CORE_OUT_REG = 0,
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parameter MEM_OUT_REG = 0,
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parameter BYTEENW = DATA_WIDTH / 8,
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parameter NUM_BATCHES = (NUM_REQS + NUM_BANKS - 1) / NUM_BANKS,
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parameter QUEUE_ADDRW = `CLOG2(QUEUE_SIZE),
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parameter BATCH_SEL_BITS = `CLOG2(NUM_BATCHES),
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parameter MEM_TAGW = MEM_TAG_ID + QUEUE_ADDRW + BATCH_SEL_BITS
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) (
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input wire clk,
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input wire reset,
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// Input request
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input wire req_valid,
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input wire req_rw,
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input wire [NUM_REQS-1:0] req_mask,
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input wire [NUM_REQS-1:0][BYTEENW-1:0] req_byteen,
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input wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr,
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input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] req_data,
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input wire [TAG_WIDTH-1:0] req_tag,
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output wire req_empty,
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output wire req_ready,
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output wire write_notify,
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// Output response
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output wire rsp_valid,
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output wire [NUM_REQS-1:0] rsp_mask,
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output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data,
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output wire [TAG_WIDTH-1:0] rsp_tag,
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output wire rsp_sop,
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output wire rsp_eop,
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input wire rsp_ready,
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// Memory request
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output wire [NUM_BANKS-1:0] mem_req_valid,
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output wire [NUM_BANKS-1:0] mem_req_rw,
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output wire [NUM_BANKS-1:0][BYTEENW-1:0] mem_req_byteen,
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output wire [NUM_BANKS-1:0][ADDR_WIDTH-1:0] mem_req_addr,
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output wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] mem_req_data,
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output wire [NUM_BANKS-1:0][MEM_TAGW-1:0]mem_req_tag,
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input wire [NUM_BANKS-1:0] mem_req_ready,
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// Memory response
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input wire [NUM_BANKS-1:0] mem_rsp_valid,
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input wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] mem_rsp_data,
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input wire [NUM_BANKS-1:0][MEM_TAGW-1:0] mem_rsp_tag,
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output wire [NUM_BANKS-1:0] mem_rsp_ready
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);
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localparam MEM_TAG_WIDTH = `UP(MEM_TAG_ID);
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localparam BATCH_SEL_WIDTH = `UP(BATCH_SEL_BITS);
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localparam TAG_ONLY_WIDTH = TAG_WIDTH - MEM_TAG_ID;
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localparam STALL_TIMEOUT = 10000000;
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`STATIC_ASSERT ((MEM_TAG_ID >= UUID_WIDTH), ("invalid parameter"))
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`STATIC_ASSERT (DATA_WIDTH == 8 * (DATA_WIDTH / 8), ("invalid parameter"))
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`STATIC_ASSERT ((0 == RSP_PARTIAL) || (1 == RSP_PARTIAL), ("invalid parameter"))
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`RUNTIME_ASSERT ((~req_valid || req_mask != 0), ("invalid request mask"));
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wire [NUM_BANKS-1:0] mem_req_valid_s;
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wire [NUM_BANKS-1:0] mem_req_mask_s;
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wire [NUM_BANKS-1:0] mem_req_rw_s;
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wire [NUM_BANKS-1:0][BYTEENW-1:0] mem_req_byteen_s;
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wire [NUM_BANKS-1:0][ADDR_WIDTH-1:0] mem_req_addr_s;
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wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] mem_req_data_s;
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wire [MEM_TAGW-1:0] mem_req_tag_s;
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wire [NUM_BANKS-1:0] mem_req_ready_s;
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wire mem_rsp_valid_s;
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wire [NUM_BANKS-1:0] mem_rsp_mask_s;
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wire [NUM_BANKS-1:0][DATA_WIDTH-1:0] mem_rsp_data_s;
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wire [MEM_TAGW-1:0] mem_rsp_tag_s;
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wire mem_rsp_ready_s;
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wire mem_rsp_fire_s;
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wire reqq_push;
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wire reqq_pop;
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wire reqq_full;
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wire reqq_empty;
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wire reqq_rw;
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wire [NUM_REQS-1:0] reqq_mask;
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wire [NUM_REQS-1:0][BYTEENW-1:0] reqq_byteen;
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wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] reqq_addr;
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wire [NUM_REQS-1:0][DATA_WIDTH-1:0] reqq_data;
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wire [QUEUE_ADDRW-1:0] reqq_tag;
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wire [MEM_TAG_WIDTH-1:0] reqq_mtid;
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wire ibuf_push;
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wire ibuf_pop;
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wire [QUEUE_ADDRW-1:0] ibuf_waddr;
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wire [QUEUE_ADDRW-1:0] ibuf_raddr;
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wire ibuf_full;
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wire ibuf_empty;
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wire [TAG_ONLY_WIDTH-1:0] ibuf_din;
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wire [TAG_ONLY_WIDTH-1:0] ibuf_dout;
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wire crsp_valid;
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wire [NUM_REQS-1:0] crsp_mask;
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wire [NUM_REQS-1:0][DATA_WIDTH-1:0] crsp_data;
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wire [TAG_WIDTH-1:0] crsp_tag;
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wire crsp_sop;
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wire crsp_eop;
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wire crsp_ready;
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// Request queue //////////////////////////////////////////////////////////
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wire req_sent_all;
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assign reqq_push = req_valid && req_ready;
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assign reqq_pop = ~reqq_empty && req_sent_all;
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wire [MEM_TAG_WIDTH-1:0] req_mtid;
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if (MEM_TAG_ID != 0) begin
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assign req_mtid = req_tag[TAG_WIDTH-1 -: MEM_TAG_ID];
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end else begin
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assign req_mtid = '0;
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end
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wire [`CLOG2(QUEUE_SIZE+1)-1:0] reqq_size;
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`UNUSED_VAR (reqq_size)
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VX_fifo_queue #(
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.DATAW (1 + NUM_REQS * (1 + BYTEENW + ADDR_WIDTH + DATA_WIDTH) + MEM_TAG_WIDTH + QUEUE_ADDRW),
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.DEPTH (QUEUE_SIZE),
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.OUT_REG (1)
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) req_queue (
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.clk (clk),
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.reset (reset),
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.push (reqq_push),
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.pop (reqq_pop),
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.data_in ({req_rw, req_mask, req_byteen, req_addr, req_data, req_mtid, ibuf_waddr}),
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.data_out ({reqq_rw, reqq_mask, reqq_byteen, reqq_addr, reqq_data, reqq_mtid, reqq_tag}),
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.full (reqq_full),
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.empty (reqq_empty),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (alm_empty),
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.size (reqq_size)
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);
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// can accept another request?
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assign req_ready = ~reqq_full && (req_rw || ~ibuf_full);
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// no pending requests
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assign req_empty = reqq_empty && ibuf_empty;
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// notify write submisison
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assign write_notify = reqq_pop && reqq_rw;
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// Index buffer ///////////////////////////////////////////////////////////
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wire rsp_complete;
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assign ibuf_push = reqq_push && ~req_rw;
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assign ibuf_pop = crsp_valid && crsp_ready && rsp_complete;
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assign ibuf_raddr = mem_rsp_tag_s[0 +: QUEUE_ADDRW];
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assign ibuf_din = req_tag[TAG_ONLY_WIDTH-1:0];
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VX_index_buffer #(
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.DATAW (TAG_ONLY_WIDTH),
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.SIZE (QUEUE_SIZE)
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) req_ibuf (
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.clk (clk),
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.reset (reset),
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.acquire_en (ibuf_push),
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.write_addr (ibuf_waddr),
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.write_data (ibuf_din),
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.read_data (ibuf_dout),
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.read_addr (ibuf_raddr),
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.release_en (ibuf_pop),
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.full (ibuf_full),
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.empty (ibuf_empty)
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);
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`UNUSED_VAR (ibuf_empty)
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// Handle memory requests /////////////////////////////////////////////////
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wire [NUM_BATCHES-1:0][NUM_BANKS-1:0] mem_req_mask_b;
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wire [NUM_BATCHES-1:0][NUM_BANKS-1:0] mem_req_rw_b;
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wire [NUM_BATCHES-1:0][NUM_BANKS-1:0][BYTEENW-1:0] mem_req_byteen_b;
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wire [NUM_BATCHES-1:0][NUM_BANKS-1:0][ADDR_WIDTH-1:0] mem_req_addr_b;
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wire [NUM_BATCHES-1:0][NUM_BANKS-1:0][DATA_WIDTH-1:0] mem_req_data_b;
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wire [BATCH_SEL_WIDTH-1:0] req_batch_idx;
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for (genvar i = 0; i < NUM_BATCHES; ++i) begin
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for (genvar j = 0; j < NUM_BANKS; ++j) begin
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localparam r = i * NUM_BANKS + j;
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if (r < NUM_REQS) begin
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assign mem_req_mask_b[i][j] = reqq_mask[r];
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assign mem_req_rw_b[i][j] = reqq_rw;
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assign mem_req_byteen_b[i][j] = reqq_byteen[r];
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assign mem_req_addr_b[i][j] = reqq_addr[r];
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assign mem_req_data_b[i][j] = reqq_data[r];
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end else begin
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assign mem_req_mask_b[i][j] = 0;
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assign mem_req_rw_b[i][j] = '0;
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assign mem_req_byteen_b[i][j] = '0;
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assign mem_req_addr_b[i][j] = '0;
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assign mem_req_data_b[i][j] = '0;
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end
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end
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end
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assign mem_req_mask_s = mem_req_mask_b[req_batch_idx];
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assign mem_req_rw_s = mem_req_rw_b[req_batch_idx];
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assign mem_req_byteen_s = mem_req_byteen_b[req_batch_idx];
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assign mem_req_addr_s = mem_req_addr_b[req_batch_idx];
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assign mem_req_data_s = mem_req_data_b[req_batch_idx];
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reg [NUM_BANKS-1:0] batch_sent_mask;
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wire [NUM_BANKS-1:0] batch_sent_mask_n = batch_sent_mask | mem_req_ready_s;
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wire batch_sent_all = (mem_req_mask_s & ~batch_sent_mask_n) == 0;
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always @(posedge clk) begin
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if (reset) begin
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batch_sent_mask <= '0;
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end else begin
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if (~reqq_empty) begin
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if (batch_sent_all) begin
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batch_sent_mask <= '0;
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end else begin
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batch_sent_mask <= batch_sent_mask_n;
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end
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end
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end
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end
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if (NUM_BATCHES > 1) begin
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reg [BATCH_SEL_BITS-1:0] req_batch_idx_r;
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always @(posedge clk) begin
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if (reset) begin
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req_batch_idx_r <= '0;
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end else begin
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if (~reqq_empty && batch_sent_all) begin
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if (req_sent_all) begin
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req_batch_idx_r <= '0;
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end else begin
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req_batch_idx_r <= req_batch_idx_r + BATCH_SEL_BITS'(1);
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end
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end
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end
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end
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wire [NUM_BATCHES-1:0] req_batch_valids;
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wire [NUM_BATCHES-1:0][BATCH_SEL_BITS-1:0] req_batch_idxs;
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wire [BATCH_SEL_BITS-1:0] req_batch_idx_last;
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for (genvar i = 0; i < NUM_BATCHES; ++i) begin
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assign req_batch_valids[i] = (| mem_req_mask_b[i]);
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assign req_batch_idxs[i] = BATCH_SEL_BITS'(i);
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end
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VX_find_first #(
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.N (NUM_BATCHES),
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.DATAW (BATCH_SEL_BITS),
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.REVERSE (1)
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) find_last (
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.valid_in (req_batch_valids),
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.data_in (req_batch_idxs),
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.data_out (req_batch_idx_last),
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`UNUSED_PIN (valid_out)
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);
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assign req_batch_idx = req_batch_idx_r;
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assign req_sent_all = batch_sent_all && (req_batch_idx_r == req_batch_idx_last);
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if (MEM_TAG_ID != 0) begin
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assign mem_req_tag_s = {reqq_mtid, req_batch_idx, reqq_tag};
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end else begin
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`UNUSED_VAR (reqq_mtid)
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assign mem_req_tag_s = {req_batch_idx, reqq_tag};
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end
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end else begin
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assign req_batch_idx = '0;
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assign req_sent_all = batch_sent_all;
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if (MEM_TAG_ID != 0) begin
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assign mem_req_tag_s = {reqq_mtid, reqq_tag};
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end else begin
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`UNUSED_VAR (reqq_mtid)
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assign mem_req_tag_s = reqq_tag;
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end
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end
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assign mem_req_valid_s = {NUM_BANKS{~reqq_empty}} & mem_req_mask_s & ~batch_sent_mask;
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for (genvar i = 0; i < NUM_BANKS; ++i) begin
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VX_elastic_buffer #(
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.DATAW (1 + BYTEENW + ADDR_WIDTH + DATA_WIDTH + MEM_TAGW),
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.SIZE (`OUT_REG_TO_EB_SIZE(MEM_OUT_REG)),
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.OUT_REG (`OUT_REG_TO_EB_REG(MEM_OUT_REG))
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) mem_req_buf (
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.clk (clk),
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.reset (reset),
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.valid_in (mem_req_valid_s[i]),
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.ready_in (mem_req_ready_s[i]),
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.data_in ({mem_req_rw_s[i], mem_req_byteen_s[i], mem_req_addr_s[i], mem_req_data_s[i], mem_req_tag_s}),
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.data_out ({mem_req_rw[i], mem_req_byteen[i], mem_req_addr[i], mem_req_data[i], mem_req_tag[i]}),
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.valid_out (mem_req_valid[i]),
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.ready_out (mem_req_ready[i])
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);
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end
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// Handle memory responses ////////////////////////////////////////////////
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reg [QUEUE_SIZE-1:0][NUM_REQS-1:0] rsp_rem_mask;
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wire [NUM_REQS-1:0] rsp_rem_mask_n, curr_mask;
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wire [BATCH_SEL_WIDTH-1:0] rsp_batch_idx;
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// Select memory response
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VX_mem_rsp_sel #(
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.NUM_REQS (NUM_BANKS),
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.DATA_WIDTH (DATA_WIDTH),
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.TAG_WIDTH (MEM_TAGW),
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.TAG_SEL_BITS (MEM_TAGW - MEM_TAG_ID),
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.OUT_REG (2)
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) mem_rsp_sel (
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.clk (clk),
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.reset (reset),
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.rsp_valid_in (mem_rsp_valid),
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.rsp_data_in (mem_rsp_data),
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.rsp_tag_in (mem_rsp_tag),
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.rsp_ready_in (mem_rsp_ready),
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.rsp_valid_out (mem_rsp_valid_s),
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.rsp_mask_out (mem_rsp_mask_s),
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.rsp_data_out (mem_rsp_data_s),
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.rsp_tag_out (mem_rsp_tag_s),
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.rsp_ready_out (mem_rsp_ready_s)
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);
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for (genvar r = 0; r < NUM_REQS; ++r) begin
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localparam i = r / NUM_BANKS;
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localparam j = r % NUM_BANKS;
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assign curr_mask[r] = (BATCH_SEL_WIDTH'(i) == rsp_batch_idx) && mem_rsp_mask_s[j];
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end
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assign rsp_rem_mask_n = rsp_rem_mask[ibuf_raddr] & ~curr_mask;
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if (NUM_BATCHES > 1) begin
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assign rsp_batch_idx = mem_rsp_tag_s[QUEUE_ADDRW +: BATCH_SEL_BITS];
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end else begin
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assign rsp_batch_idx = '0;
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end
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assign rsp_complete = ~(| rsp_rem_mask_n);
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always @(posedge clk) begin
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if (ibuf_push) begin
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rsp_rem_mask[ibuf_waddr] <= req_mask;
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end
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if (mem_rsp_fire_s) begin
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rsp_rem_mask[ibuf_raddr] <= rsp_rem_mask_n;
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end
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end
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assign mem_rsp_fire_s = mem_rsp_valid_s && mem_rsp_ready_s;
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if (RSP_PARTIAL == 1) begin
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reg [QUEUE_SIZE-1:0] rsp_sop_r;
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always @(posedge clk) begin
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if (ibuf_push) begin
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rsp_sop_r[ibuf_waddr] <= 1;
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end
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if (mem_rsp_fire_s) begin
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rsp_sop_r[ibuf_raddr] <= 0;
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end
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end
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assign mem_rsp_ready_s = crsp_ready;
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assign crsp_valid = mem_rsp_valid_s;
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assign crsp_mask = curr_mask;
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assign crsp_sop = rsp_sop_r[ibuf_raddr];
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for (genvar r = 0; r < NUM_REQS; ++r) begin
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localparam j = r % NUM_BANKS;
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assign crsp_data[r] = mem_rsp_data_s[j];
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end
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end else begin
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reg [NUM_BATCHES*NUM_BANKS*DATA_WIDTH-1:0] rsp_store [QUEUE_SIZE-1:0];
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reg [NUM_BATCHES*NUM_BANKS*DATA_WIDTH-1:0] rsp_store_n;
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reg [NUM_REQS-1:0] rsp_orig_mask [QUEUE_SIZE-1:0];
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always @(*) begin
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rsp_store_n = rsp_store[ibuf_raddr];
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for (integer i = 0; i < NUM_BANKS; ++i) begin
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if ((NUM_BANKS == 1) || mem_rsp_mask_s[i]) begin
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rsp_store_n[(rsp_batch_idx * NUM_BANKS + i) * DATA_WIDTH +: DATA_WIDTH] = mem_rsp_data_s[i];
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if (ibuf_push) begin
|
|
rsp_orig_mask[ibuf_waddr] <= req_mask;
|
|
end
|
|
if (mem_rsp_valid_s) begin
|
|
rsp_store[ibuf_raddr] <= rsp_store_n;
|
|
end
|
|
end
|
|
|
|
assign mem_rsp_ready_s = crsp_ready || ~rsp_complete;
|
|
|
|
assign crsp_valid = mem_rsp_valid_s && rsp_complete;
|
|
|
|
assign crsp_mask = rsp_orig_mask[ibuf_raddr];
|
|
assign crsp_sop = 1'b1;
|
|
|
|
for (genvar r = 0; r < NUM_REQS; ++r) begin
|
|
localparam i = r / NUM_BANKS;
|
|
localparam j = r % NUM_BANKS;
|
|
assign crsp_data[r] = rsp_store_n[(i * NUM_BANKS + j) * DATA_WIDTH +: DATA_WIDTH];
|
|
end
|
|
end
|
|
|
|
if (MEM_TAG_ID != 0) begin
|
|
assign crsp_tag = {mem_rsp_tag_s[MEM_TAGW-1 -: MEM_TAG_ID], ibuf_dout};
|
|
end else begin
|
|
assign crsp_tag = ibuf_dout;
|
|
end
|
|
|
|
assign crsp_eop = ibuf_pop;
|
|
|
|
// Send response to caller
|
|
|
|
VX_elastic_buffer #(
|
|
.DATAW (NUM_REQS + 1 + 1 + (NUM_REQS * DATA_WIDTH) + TAG_WIDTH),
|
|
.SIZE (`OUT_REG_TO_EB_SIZE(CORE_OUT_REG)),
|
|
.OUT_REG (`OUT_REG_TO_EB_REG(CORE_OUT_REG))
|
|
) rsp_buf (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.valid_in (crsp_valid),
|
|
.ready_in (crsp_ready),
|
|
.data_in ({crsp_mask, crsp_sop, crsp_eop, crsp_data, crsp_tag}),
|
|
.data_out ({rsp_mask, rsp_sop, rsp_eop, rsp_data, rsp_tag}),
|
|
.valid_out (rsp_valid),
|
|
.ready_out (rsp_ready)
|
|
);
|
|
|
|
`ifdef SIMULATION
|
|
wire [`UP(UUID_WIDTH)-1:0] req_dbg_uuid;
|
|
wire [`UP(UUID_WIDTH)-1:0] rsp_dbg_uuid;
|
|
wire [`UP(UUID_WIDTH)-1:0] mem_req_dbg_uuid;
|
|
wire [`UP(UUID_WIDTH)-1:0] mem_rsp_dbg_uuid;
|
|
|
|
if (UUID_WIDTH != 0) begin
|
|
assign req_dbg_uuid = req_tag[TAG_WIDTH-1 -: UUID_WIDTH];
|
|
assign rsp_dbg_uuid = rsp_tag[TAG_WIDTH-1 -: UUID_WIDTH];
|
|
assign mem_req_dbg_uuid = reqq_mtid[MEM_TAG_ID-1 -: UUID_WIDTH];
|
|
assign mem_rsp_dbg_uuid = mem_rsp_tag_s[MEM_TAGW-1 -: UUID_WIDTH];
|
|
end else begin
|
|
assign req_dbg_uuid = '0;
|
|
assign rsp_dbg_uuid = '0;
|
|
assign mem_req_dbg_uuid = '0;
|
|
assign mem_rsp_dbg_uuid = '0;
|
|
end
|
|
|
|
`UNUSED_VAR (req_dbg_uuid)
|
|
`UNUSED_VAR (rsp_dbg_uuid)
|
|
`UNUSED_VAR (mem_req_dbg_uuid)
|
|
`UNUSED_VAR (mem_rsp_dbg_uuid)
|
|
|
|
reg [(`UP(UUID_WIDTH) + TAG_ONLY_WIDTH + 64)-1:0] pending_reqs [QUEUE_SIZE-1:0];
|
|
reg [QUEUE_SIZE-1:0] pending_req_valids;
|
|
|
|
always @(posedge clk) begin
|
|
if (reset) begin
|
|
pending_req_valids <= '0;
|
|
end else begin
|
|
if (ibuf_push) begin
|
|
pending_req_valids[ibuf_waddr] <= 1'b1;
|
|
end
|
|
if (ibuf_pop) begin
|
|
pending_req_valids[ibuf_raddr] <= 1'b0;
|
|
end
|
|
end
|
|
|
|
if (ibuf_push) begin
|
|
pending_reqs[ibuf_waddr] <= {req_dbg_uuid, ibuf_din, $time};
|
|
end
|
|
|
|
for (integer i = 0; i < QUEUE_SIZE; ++i) begin
|
|
if (pending_req_valids[i]) begin
|
|
`ASSERT(($time - pending_reqs[i][0 +: 64]) < STALL_TIMEOUT,
|
|
("%t: *** %s response timeout: remaining=%b, tag=0x%0h (#%0d)",
|
|
$time, INST_ID, rsp_rem_mask[i], pending_reqs[i][64 +: TAG_ONLY_WIDTH], pending_reqs[i][64+TAG_ONLY_WIDTH +: `UP(UUID_WIDTH)]));
|
|
end
|
|
end
|
|
end
|
|
`endif
|
|
|
|
///////////////////////////////////////////////////////////////////////////
|
|
|
|
`ifndef NDEBUG
|
|
wire [NUM_BANKS-1:0] mem_req_fire_s = mem_req_valid_s & mem_req_ready_s;
|
|
always @(negedge clk) begin
|
|
if (!reset) begin
|
|
if (req_valid && req_ready) begin
|
|
if (req_rw) begin
|
|
`TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));
|
|
`TRACE_ARRAY1D(1, req_addr, NUM_REQS);
|
|
`TRACE(1, (", byteen="));
|
|
`TRACE_ARRAY1D(1, req_byteen, NUM_REQS);
|
|
`TRACE(1, (", data="));
|
|
`TRACE_ARRAY1D(1, req_data, NUM_REQS);
|
|
end else begin
|
|
`TRACE(1, ("%d: %s-core-req-rd: valid=%b, addr=", $time, INST_ID, req_mask));
|
|
`TRACE_ARRAY1D(1, req_addr, NUM_REQS);
|
|
end
|
|
`TRACE(1, (", tag=0x%0h, tag_only=0x%0h (#%0d)\n", req_tag, req_tag[TAG_ONLY_WIDTH-1:0], req_dbg_uuid));
|
|
end
|
|
if (rsp_valid && rsp_ready) begin
|
|
`TRACE(1, ("%d: %s-rsp: valid=%b, sop=%b, eop=%b, data=", $time, INST_ID, rsp_mask, rsp_sop, rsp_eop));
|
|
`TRACE_ARRAY1D(1, rsp_data, NUM_REQS);
|
|
`TRACE(1, (", tag=0x%0h, tag_only=0x%0h (#%0d)\n", rsp_tag, rsp_tag[TAG_ONLY_WIDTH-1:0], rsp_dbg_uuid));
|
|
end
|
|
if (| mem_req_fire_s) begin
|
|
if (| mem_req_rw_s) begin
|
|
`TRACE(1, ("%d: %s-mem-req-wr: valid=%b, addr=", $time, INST_ID, mem_req_fire_s));
|
|
`TRACE_ARRAY1D(1, mem_req_addr_s, NUM_BANKS);
|
|
`TRACE(1, (", byteen="));
|
|
`TRACE_ARRAY1D(1, mem_req_byteen_s, NUM_BANKS);
|
|
`TRACE(1, (", data="));
|
|
`TRACE_ARRAY1D(1, mem_req_data_s, NUM_BANKS);
|
|
end else begin
|
|
`TRACE(1, ("%d: %s-mem-req-rd: valid=%b, addr=", $time, INST_ID, mem_req_fire_s));
|
|
`TRACE_ARRAY1D(1, mem_req_addr_s, NUM_BANKS);
|
|
end
|
|
`TRACE(1, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_waddr, req_batch_idx, mem_req_dbg_uuid));
|
|
end
|
|
if (mem_rsp_fire_s) begin
|
|
`TRACE(1, ("%d: %s-mem-rsp: valid=%b, data=", $time, INST_ID, mem_rsp_mask_s));
|
|
`TRACE_ARRAY1D(1, mem_rsp_data_s, NUM_BANKS);
|
|
`TRACE(1, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_raddr, rsp_batch_idx, mem_rsp_dbg_uuid));
|
|
end
|
|
end
|
|
end
|
|
`else
|
|
always @(negedge clk) begin
|
|
if (!reset) begin
|
|
if (req_valid && req_ready) begin
|
|
if (req_rw) begin
|
|
`TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));
|
|
`TRACE_ARRAY1D(1, req_addr, NUM_REQS);
|
|
`TRACE(1, (", byteen="));
|
|
`TRACE_ARRAY1D(1, req_byteen, NUM_REQS);
|
|
`TRACE(1, (", data="));
|
|
`TRACE_ARRAY1D(1, req_data, NUM_REQS);
|
|
end else begin
|
|
`TRACE(1, ("%d: %s-core-req-rd: valid=%b, addr=", $time, INST_ID, req_mask));
|
|
`TRACE_ARRAY1D(1, req_addr, NUM_REQS);
|
|
end
|
|
`TRACE(1, (", tag=0x%0h, tag_only=0x%0h\n", req_tag, req_tag[TAG_ONLY_WIDTH-1:0]));
|
|
end
|
|
if (rsp_valid && rsp_ready) begin
|
|
`TRACE(1, ("%d: %s-rsp: valid=%b, sop=%b, eop=%b, data=", $time, INST_ID, rsp_mask, rsp_sop, rsp_eop));
|
|
`TRACE_ARRAY1D(1, rsp_data, NUM_REQS);
|
|
`TRACE(1, (", tag=0x%0h, tag_only=0x%0h\n", rsp_tag, rsp_tag[TAG_ONLY_WIDTH-1:0]));
|
|
end
|
|
end
|
|
end
|
|
`endif
|
|
|
|
endmodule
|
|
`TRACING_ON
|