Disable trace during the very start of simulation

hw/rtl/VX_platform.vh

@@ -144,6 +144,9 @@
                         x \
                         /* verilator lint_on UNUSED */
 `define TRACE(level, args) dpi_trace(level, $sformatf args)
+// squelch spurrious traces at the very first few cycles caused by to reset
+// delay
+`define TRACE_STARTTIME 32'd10
 `endif
 // NOTE(hansung): define these macros to be the same as VERILATOR under VCS;
 // they will mostly be ignored
@@ -209,7 +212,9 @@
                         x \
                         /* verilator lint_on UNUSED */
 `define TRACE(level, args) $write args
-// `define TRACE(level, args) dpi_trace(level, $sformatf args)
+// squelch spurrious traces at the very first few cycles caused by to reset
+// delay
+`define TRACE_STARTTIME 32'd10
 `endif
 `endif
 

hw/rtl/core/VX_commit.sv

@@ -242,6 +242,7 @@ module VX_commit import VX_gpu_pkg::*; #(
 `ifdef DBG_TRACE_CORE_PIPELINE_VCS
     for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
         always @(posedge clk) begin
+            if (!reset && ($time > `TRACE_STARTTIME)) begin
                 if (alu_commit_if[i].valid && alu_commit_if[i].ready) begin
                     `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, alu_commit_if[i].data.wid, alu_commit_if[i].data.PC, alu_commit_if[i].data.tmask, alu_commit_if[i].data.wb, alu_commit_if[i].data.rd, alu_commit_if[i].data.sop, alu_commit_if[i].data.eop));
                     `TRACE_ARRAY1D(1, alu_commit_if[i].data.data, `NUM_THREADS);
@@ -266,6 +267,7 @@ module VX_commit import VX_gpu_pkg::*; #(
                 end
             end
         end
+    end
 `endif
 
 endmodule

hw/rtl/core/VX_decode.sv

@@ -587,6 +587,7 @@ module VX_decode  #(
 
 `ifdef DBG_TRACE_CORE_PIPELINE_VCS
     always @(posedge clk) begin
+        if (!reset && ($time > `TRACE_STARTTIME)) begin
             if (decode_if.valid && decode_if.ready) begin
                 `TRACE(1, ("%d: core%0d-decode: wid=%0d, PC=0x%0h, instr=0x%0h, ex=", $time, CORE_ID, decode_if.data.wid, decode_if.data.PC, instr));
                 trace_ex_type(1, decode_if.data.ex_type);
@@ -596,6 +597,7 @@ module VX_decode  #(
                     decode_if.data.op_mod, decode_if.data.tmask, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3, decode_if.data.imm, use_rd, use_rs1, use_rs2, use_rs3, decode_if.data.use_PC, decode_if.data.use_imm, decode_if.data.uuid));
             end
         end
+    end
 `endif
 
 endmodule

hw/rtl/core/VX_dispatch.sv

@@ -308,6 +308,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
 `ifdef DBG_TRACE_CORE_PIPELINE_VCS
     for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
         always @(posedge clk) begin
+            if (!reset && ($time > `TRACE_STARTTIME)) begin
                 if (operands_if[i].valid && operands_if[i].ready) begin
                     `TRACE(1, ("%d: core%0d-issue: wid=%0d, PC=0x%0h, ex=", $time, CORE_ID, wis_to_wid(operands_if[i].data.wis, i), operands_if[i].data.PC));
                     trace_ex_type(1, operands_if[i].data.ex_type);
@@ -321,6 +322,7 @@ module VX_dispatch import VX_gpu_pkg::*; #(
                 end
             end
         end
+    end
 `endif
 
 endmodule

hw/rtl/libs/VX_mem_scheduler.sv

@@ -533,7 +533,7 @@ module VX_mem_scheduler #(
 `ifndef NDEBUG
     wire [NUM_BANKS-1:0] mem_req_fire_s = mem_req_valid_s & mem_req_ready_s;
     always @(negedge clk) begin
-        if (!reset) begin
+        if (!reset && ($time > `TRACE_STARTTIME)) begin
             if (req_valid && req_ready) begin
                 if (req_rw) begin
                     `TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));
@@ -576,7 +576,7 @@ module VX_mem_scheduler #(
     end
 `else
     always @(negedge clk) begin
-        if (!reset) begin
+        if (!reset && ($time > `TRACE_STARTTIME)) begin
             if (req_valid && req_ready) begin
                 if (req_rw) begin
                     `TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));