diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh
index 7a26c968..d5ad6c4f 100644
--- a/hw/rtl/VX_platform.vh
+++ b/hw/rtl/VX_platform.vh
@@ -144,6 +144,9 @@
                         x \
                         /* verilator lint_on UNUSED */
 `define TRACE(level, args) dpi_trace(level, $sformatf args)
+// squelch spurrious traces at the very first few cycles caused by to reset
+// delay
+`define TRACE_STARTTIME 32'd10
 `endif
 // NOTE(hansung): define these macros to be the same as VERILATOR under VCS;
 // they will mostly be ignored
@@ -209,7 +212,9 @@
                         x \
                         /* verilator lint_on UNUSED */
 `define TRACE(level, args) $write args
-// `define TRACE(level, args) dpi_trace(level, $sformatf args)
+// squelch spurrious traces at the very first few cycles caused by to reset
+// delay
+`define TRACE_STARTTIME 32'd10
 `endif
 `endif
 
diff --git a/hw/rtl/core/VX_commit.sv b/hw/rtl/core/VX_commit.sv
index 6647a648..f417d64f 100644
--- a/hw/rtl/core/VX_commit.sv
+++ b/hw/rtl/core/VX_commit.sv
@@ -242,27 +242,29 @@ module VX_commit import VX_gpu_pkg::*; #(
 `ifdef DBG_TRACE_CORE_PIPELINE_VCS
     for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin
         always @(posedge clk) begin
-            if (alu_commit_if[i].valid && alu_commit_if[i].ready) begin
-                `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, alu_commit_if[i].data.wid, alu_commit_if[i].data.PC, alu_commit_if[i].data.tmask, alu_commit_if[i].data.wb, alu_commit_if[i].data.rd, alu_commit_if[i].data.sop, alu_commit_if[i].data.eop));
-                `TRACE_ARRAY1D(1, alu_commit_if[i].data.data, `NUM_THREADS);
-                `TRACE(1, (" (#%0d)\n", alu_commit_if[i].data.uuid));
-            end
-            if (lsu_commit_if[i].valid && lsu_commit_if[i].ready) begin
-                `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, lsu_commit_if[i].data.wid, lsu_commit_if[i].data.PC, lsu_commit_if[i].data.tmask, lsu_commit_if[i].data.wb, lsu_commit_if[i].data.rd, lsu_commit_if[i].data.sop, lsu_commit_if[i].data.eop));
-                `TRACE_ARRAY1D(1, lsu_commit_if[i].data.data, `NUM_THREADS);
-                `TRACE(1, (" (#%0d)\n", lsu_commit_if[i].data.uuid));
-            end
-        `ifdef EXT_F_ENABLE
-            if (fpu_commit_if[i].valid && fpu_commit_if[i].ready) begin
-                `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=FPU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, fpu_commit_if[i].data.wid, fpu_commit_if[i].data.PC, fpu_commit_if[i].data.tmask, fpu_commit_if[i].data.wb, fpu_commit_if[i].data.rd, fpu_commit_if[i].data.sop, fpu_commit_if[i].data.eop));
-                `TRACE_ARRAY1D(1, fpu_commit_if[i].data.data, `NUM_THREADS);
-                `TRACE(1, (" (#%0d)\n", fpu_commit_if[i].data.uuid));
-            end
-        `endif
-            if (sfu_commit_if[i].valid && sfu_commit_if[i].ready) begin
-                `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=SFU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, sfu_commit_if[i].data.wid, sfu_commit_if[i].data.PC, sfu_commit_if[i].data.tmask, sfu_commit_if[i].data.wb, sfu_commit_if[i].data.rd, sfu_commit_if[i].data.sop, sfu_commit_if[i].data.eop));
-                `TRACE_ARRAY1D(1, sfu_commit_if[i].data.data, `NUM_THREADS);
-                `TRACE(1, (" (#%0d)\n", sfu_commit_if[i].data.uuid));
+            if (!reset && ($time > `TRACE_STARTTIME)) begin
+                if (alu_commit_if[i].valid && alu_commit_if[i].ready) begin
+                    `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=ALU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, alu_commit_if[i].data.wid, alu_commit_if[i].data.PC, alu_commit_if[i].data.tmask, alu_commit_if[i].data.wb, alu_commit_if[i].data.rd, alu_commit_if[i].data.sop, alu_commit_if[i].data.eop));
+                    `TRACE_ARRAY1D(1, alu_commit_if[i].data.data, `NUM_THREADS);
+                    `TRACE(1, (" (#%0d)\n", alu_commit_if[i].data.uuid));
+                end
+                if (lsu_commit_if[i].valid && lsu_commit_if[i].ready) begin
+                    `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=LSU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, lsu_commit_if[i].data.wid, lsu_commit_if[i].data.PC, lsu_commit_if[i].data.tmask, lsu_commit_if[i].data.wb, lsu_commit_if[i].data.rd, lsu_commit_if[i].data.sop, lsu_commit_if[i].data.eop));
+                    `TRACE_ARRAY1D(1, lsu_commit_if[i].data.data, `NUM_THREADS);
+                    `TRACE(1, (" (#%0d)\n", lsu_commit_if[i].data.uuid));
+                end
+            `ifdef EXT_F_ENABLE
+                if (fpu_commit_if[i].valid && fpu_commit_if[i].ready) begin
+                    `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=FPU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, fpu_commit_if[i].data.wid, fpu_commit_if[i].data.PC, fpu_commit_if[i].data.tmask, fpu_commit_if[i].data.wb, fpu_commit_if[i].data.rd, fpu_commit_if[i].data.sop, fpu_commit_if[i].data.eop));
+                    `TRACE_ARRAY1D(1, fpu_commit_if[i].data.data, `NUM_THREADS);
+                    `TRACE(1, (" (#%0d)\n", fpu_commit_if[i].data.uuid));
+                end
+            `endif
+                if (sfu_commit_if[i].valid && sfu_commit_if[i].ready) begin
+                    `TRACE(1, ("%d: core%0d-commit: wid=%0d, PC=0x%0h, ex=SFU, tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", $time, CORE_ID, sfu_commit_if[i].data.wid, sfu_commit_if[i].data.PC, sfu_commit_if[i].data.tmask, sfu_commit_if[i].data.wb, sfu_commit_if[i].data.rd, sfu_commit_if[i].data.sop, sfu_commit_if[i].data.eop));
+                    `TRACE_ARRAY1D(1, sfu_commit_if[i].data.data, `NUM_THREADS);
+                    `TRACE(1, (" (#%0d)\n", sfu_commit_if[i].data.uuid));
+                end
             end
         end
     end
diff --git a/hw/rtl/core/VX_decode.sv b/hw/rtl/core/VX_decode.sv
index 2ca414cd..cf21d72f 100644
--- a/hw/rtl/core/VX_decode.sv
+++ b/hw/rtl/core/VX_decode.sv
@@ -587,13 +587,15 @@ module VX_decode  #(
 
 `ifdef DBG_TRACE_CORE_PIPELINE_VCS
     always @(posedge clk) begin
-        if (decode_if.valid && decode_if.ready) begin
-            `TRACE(1, ("%d: core%0d-decode: wid=%0d, PC=0x%0h, instr=0x%0h, ex=", $time, CORE_ID, decode_if.data.wid, decode_if.data.PC, instr));
-            trace_ex_type(1, decode_if.data.ex_type);
-            `TRACE(1, (", op="));
-            trace_ex_op(1, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod, decode_if.data.rd, decode_if.data.rs2, decode_if.data.use_imm, decode_if.data.imm);
-            `TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=0x%0h, opds=%b%b%b%b, use_pc=%b, use_imm=%b (#%0d)\n",
-                decode_if.data.op_mod, decode_if.data.tmask, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3, decode_if.data.imm, use_rd, use_rs1, use_rs2, use_rs3, decode_if.data.use_PC, decode_if.data.use_imm, decode_if.data.uuid));
+        if (!reset && ($time > `TRACE_STARTTIME)) begin
+            if (decode_if.valid && decode_if.ready) begin
+                `TRACE(1, ("%d: core%0d-decode: wid=%0d, PC=0x%0h, instr=0x%0h, ex=", $time, CORE_ID, decode_if.data.wid, decode_if.data.PC, instr));
+                trace_ex_type(1, decode_if.data.ex_type);
+                `TRACE(1, (", op="));
+                trace_ex_op(1, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod, decode_if.data.rd, decode_if.data.rs2, decode_if.data.use_imm, decode_if.data.imm);
+                `TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=0x%0h, opds=%b%b%b%b, use_pc=%b, use_imm=%b (#%0d)\n",
+                    decode_if.data.op_mod, decode_if.data.tmask, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3, decode_if.data.imm, use_rd, use_rs1, use_rs2, use_rs3, decode_if.data.use_PC, decode_if.data.use_imm, decode_if.data.uuid));
+            end
         end
     end
 `endif
diff --git a/hw/rtl/core/VX_dispatch.sv b/hw/rtl/core/VX_dispatch.sv
index 0f47b752..29f07a18 100644
--- a/hw/rtl/core/VX_dispatch.sv
+++ b/hw/rtl/core/VX_dispatch.sv
@@ -308,16 +308,18 @@ module VX_dispatch import VX_gpu_pkg::*; #(
 `ifdef DBG_TRACE_CORE_PIPELINE_VCS
     for (genvar i=0; i < `ISSUE_WIDTH; ++i) begin
         always @(posedge clk) begin
-            if (operands_if[i].valid && operands_if[i].ready) begin
-                `TRACE(1, ("%d: core%0d-issue: wid=%0d, PC=0x%0h, ex=", $time, CORE_ID, wis_to_wid(operands_if[i].data.wis, i), operands_if[i].data.PC));
-                trace_ex_type(1, operands_if[i].data.ex_type);
-                `TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1_data=", operands_if[i].data.op_mod, operands_if[i].data.tmask, operands_if[i].data.wb, operands_if[i].data.rd));
-                `TRACE_ARRAY1D(1, operands_if[i].data.rs1_data, `NUM_THREADS);
-                `TRACE(1, (", rs2_data="));
-                `TRACE_ARRAY1D(1, operands_if[i].data.rs2_data, `NUM_THREADS);
-                `TRACE(1, (", rs3_data="));
-                `TRACE_ARRAY1D(1, operands_if[i].data.rs3_data, `NUM_THREADS);
-                `TRACE(1, (" (#%0d)\n", operands_if[i].data.uuid));
+            if (!reset && ($time > `TRACE_STARTTIME)) begin
+                if (operands_if[i].valid && operands_if[i].ready) begin
+                    `TRACE(1, ("%d: core%0d-issue: wid=%0d, PC=0x%0h, ex=", $time, CORE_ID, wis_to_wid(operands_if[i].data.wis, i), operands_if[i].data.PC));
+                    trace_ex_type(1, operands_if[i].data.ex_type);
+                    `TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1_data=", operands_if[i].data.op_mod, operands_if[i].data.tmask, operands_if[i].data.wb, operands_if[i].data.rd));
+                    `TRACE_ARRAY1D(1, operands_if[i].data.rs1_data, `NUM_THREADS);
+                    `TRACE(1, (", rs2_data="));
+                    `TRACE_ARRAY1D(1, operands_if[i].data.rs2_data, `NUM_THREADS);
+                    `TRACE(1, (", rs3_data="));
+                    `TRACE_ARRAY1D(1, operands_if[i].data.rs3_data, `NUM_THREADS);
+                    `TRACE(1, (" (#%0d)\n", operands_if[i].data.uuid));
+                end
             end
         end
     end
diff --git a/hw/rtl/libs/VX_mem_scheduler.sv b/hw/rtl/libs/VX_mem_scheduler.sv
index 1734c720..ae34812b 100644
--- a/hw/rtl/libs/VX_mem_scheduler.sv
+++ b/hw/rtl/libs/VX_mem_scheduler.sv
@@ -533,7 +533,7 @@ module VX_mem_scheduler #(
 `ifndef NDEBUG
     wire [NUM_BANKS-1:0] mem_req_fire_s = mem_req_valid_s & mem_req_ready_s;
     always @(negedge clk) begin
-        if (!reset) begin
+        if (!reset && ($time > `TRACE_STARTTIME)) begin
             if (req_valid && req_ready) begin
                 if (req_rw) begin
                     `TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));
@@ -576,7 +576,7 @@ module VX_mem_scheduler #(
     end
 `else
     always @(negedge clk) begin
-        if (!reset) begin
+        if (!reset && ($time > `TRACE_STARTTIME)) begin
             if (req_valid && req_ready) begin
                 if (req_rw) begin
                     `TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));