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Disable trace during the very start of simulation

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This commit is contained in:
Hansung Kim
2024-08-13 16:01:12 -07:00
parent d39e24643d
commit 1410b39143
5 changed files with 52 additions and 41 deletions
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4
hw/rtl/libs/VX_mem_scheduler.sv
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@@ -533,7 +533,7 @@ module VX_mem_scheduler #(
`ifndef NDEBUG
wire [NUM_BANKS-1:0] mem_req_fire_s = mem_req_valid_s & mem_req_ready_s;
always @(negedge clk) begin
if (!reset) begin
if (!reset && ($time > `TRACE_STARTTIME)) begin
if (req_valid && req_ready) begin
if (req_rw) begin
`TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));
@@ -576,7 +576,7 @@ module VX_mem_scheduler #(
end
`else
always @(negedge clk) begin
if (!reset) begin
if (!reset && ($time > `TRACE_STARTTIME)) begin
if (req_valid && req_ready) begin
if (req_rw) begin
`TRACE(1, ("%d: %s-core-req-wr: valid=%b, addr=", $time, INST_ID, req_mask));