Disable trace during the very start of simulation

This commit is contained in:
Hansung Kim
2024-08-13 16:01:12 -07:00
parent d39e24643d
commit 1410b39143
5 changed files with 52 additions and 41 deletions

View File

@@ -144,6 +144,9 @@
x \
/* verilator lint_on UNUSED */
`define TRACE(level, args) dpi_trace(level, $sformatf args)
// squelch spurrious traces at the very first few cycles caused by to reset
// delay
`define TRACE_STARTTIME 32'd10
`endif
// NOTE(hansung): define these macros to be the same as VERILATOR under VCS;
// they will mostly be ignored
@@ -209,7 +212,9 @@
x \
/* verilator lint_on UNUSED */
`define TRACE(level, args) $write args
// `define TRACE(level, args) dpi_trace(level, $sformatf args)
// squelch spurrious traces at the very first few cycles caused by to reset
// delay
`define TRACE_STARTTIME 32'd10
`endif
`endif