force random values for unitialized signals

2020-05-20 20:57:15 -04:00
parent 7e5fed3ec1
commit 1102871180
3 changed files with 17 additions and 1 deletions
--- a/hw/simulate/simulator.cpp
+++ b/hw/simulate/simulator.cpp
@@ -9,6 +9,14 @@ double sc_time_stamp() {
 }

 Simulator::Simulator() {    
+  // force random values for unitialized signals
+  const char* args[] = {"", "+verilator+rand+reset+2", "+verilator+seed+0"};
+  Verilated::commandArgs(3, args);
+
+#ifndef NDEBUG
+  Verilated::debug(1);
+#endif
+
  ram_ = nullptr;
  vortex_ = new VVortex_Socket();