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mrvq update ready + init ready as 1 in same cycle causing incorrect ready state

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This commit is contained in:
felsabbagh3
2020-05-16 18:52:30 -07:00
parent 794664363c
commit 101de6b138
3 changed files with 53 additions and 31 deletions
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15
hw/rtl/cache/VX_cache.v vendored
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@@ -128,12 +128,17 @@ module VX_cache #(
);
`DEBUG_BEGIN
wire[31:0] debug_core_req_use_pc;
wire[1:0] debug_core_req_wb;
wire[4:0] debug_core_req_rd;
wire[`NW_BITS-1:0] debug_core_req_warp_num;
assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0];
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
wire[31:0] debug_core_req_use_pc;
wire[1:0] debug_core_req_wb;
wire[4:0] debug_core_req_rd;
wire[`NW_BITS-1:0] debug_core_req_warp_num;
assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0];
end
`DEBUG_END