From 101de6b13881fc9e654291a5b13c988ce60fda41 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sat, 16 May 2020 18:52:30 -0700 Subject: [PATCH] mrvq update ready + init ready as 1 in same cycle causing incorrect ready state --- hw/rtl/cache/VX_bank.v | 55 +++++++++++++++++------------- hw/rtl/cache/VX_cache.v | 15 +++++--- hw/rtl/cache/VX_cache_miss_resrv.v | 14 ++++++-- 3 files changed, 53 insertions(+), 31 deletions(-) diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index adc733f9..1820784f 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -105,31 +105,32 @@ module VX_bank #( ); `DEBUG_BEGIN - wire[31:0] debug_use_pc_st0; - wire[1:0] debug_wb_st0; - wire[4:0] debug_rd_st0; - wire[`NW_BITS-1:0] debug_warp_num_st0; - wire[2:0] debug_mem_read_st0; - wire[2:0] debug_mem_write_st0; - wire[`REQS_BITS-1:0] debug_tid_st0; + + wire[31:0] debug_use_pc_st0; + wire[1:0] debug_wb_st0; + wire[4:0] debug_rd_st0; + wire[`NW_BITS-1:0] debug_warp_num_st0; + wire[2:0] debug_mem_read_st0; + wire[2:0] debug_mem_write_st0; + wire[`REQS_BITS-1:0] debug_tid_st0; - wire[31:0] debug_use_pc_st1e; - wire[1:0] debug_wb_st1e; - wire[4:0] debug_rd_st1e; - wire[`NW_BITS-1:0] debug_warp_num_st1e; - wire[2:0] debug_mem_read_st1e; - wire[2:0] debug_mem_write_st1e; - wire[`REQS_BITS-1:0] debug_tid_st1e; + wire[31:0] debug_use_pc_st1e; + wire[1:0] debug_wb_st1e; + wire[4:0] debug_rd_st1e; + wire[`NW_BITS-1:0] debug_warp_num_st1e; + wire[2:0] debug_mem_read_st1e; + wire[2:0] debug_mem_write_st1e; + wire[`REQS_BITS-1:0] debug_tid_st1e; - wire[31:0] debug_use_pc_st2; - wire[1:0] debug_wb_st2; - wire[4:0] debug_rd_st2; - wire[`NW_BITS-1:0] debug_warp_num_st2; - wire[2:0] debug_mem_read_st2; - wire[2:0] debug_mem_write_st2; - wire[`REQS_BITS-1:0] debug_tid_st2; + wire[31:0] debug_use_pc_st2; + wire[1:0] debug_wb_st2; + wire[4:0] debug_rd_st2; + wire[`NW_BITS-1:0] debug_warp_num_st2; + wire[2:0] debug_mem_read_st2; + wire[2:0] debug_mem_write_st2; + wire[`REQS_BITS-1:0] debug_tid_st2; `DEBUG_END @@ -340,7 +341,9 @@ module VX_bank #( assign qual_from_mrvq_st0 = mrvq_pop; `DEBUG_BEGIN - assign {debug_use_pc_st0, debug_wb_st0, debug_rd_st0, debug_warp_num_st0, debug_mem_read_st0, debug_mem_write_st0, debug_tid_st0} = qual_inst_meta_st0; + if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin + assign {debug_use_pc_st0, debug_wb_st0, debug_rd_st0, debug_warp_num_st0, debug_mem_read_st0, debug_mem_write_st0, debug_tid_st0} = qual_inst_meta_st0; + end `DEBUG_END VX_generic_register #( @@ -436,7 +439,9 @@ module VX_bank #( ); `DEBUG_BEGIN - assign {debug_use_pc_st1e, debug_wb_st1e, debug_rd_st1e, debug_warp_num_st1e, debug_mem_read_st1e, debug_mem_write_st1e, debug_tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1]; + if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin + assign {debug_use_pc_st1e, debug_wb_st1e, debug_rd_st1e, debug_warp_num_st1e, debug_mem_read_st1e, debug_mem_write_st1e, debug_tid_st1e} = inst_meta_st1[STAGE_1_CYCLES-1]; + end `DEBUG_END wire qual_valid_st1e_2 = valid_st1[STAGE_1_CYCLES-1] && !is_fill_st1[STAGE_1_CYCLES-1]; @@ -467,7 +472,9 @@ module VX_bank #( ); `DEBUG_BEGIN - assign {debug_use_pc_st2, debug_wb_st2, debug_rd_st2, debug_warp_num_st2, debug_mem_read_st2, debug_mem_write_st2, debug_tid_st2} = inst_meta_st2; + if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin + assign {debug_use_pc_st2, debug_wb_st2, debug_rd_st2, debug_warp_num_st2, debug_mem_read_st2, debug_mem_write_st2, debug_tid_st2} = inst_meta_st2; + end `DEBUG_END // Enqueue to miss reserv if it's a valid miss diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index a58ba9f3..5588d3c1 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -128,12 +128,17 @@ module VX_cache #( ); `DEBUG_BEGIN - wire[31:0] debug_core_req_use_pc; - wire[1:0] debug_core_req_wb; - wire[4:0] debug_core_req_rd; - wire[`NW_BITS-1:0] debug_core_req_warp_num; - assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0]; + if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin + + wire[31:0] debug_core_req_use_pc; + wire[1:0] debug_core_req_wb; + wire[4:0] debug_core_req_rd; + wire[`NW_BITS-1:0] debug_core_req_warp_num; + + assign {debug_core_req_use_pc, debug_core_req_wb, debug_core_req_rd, debug_core_req_warp_num} = core_req_tag[0]; + + end `DEBUG_END diff --git a/hw/rtl/cache/VX_cache_miss_resrv.v b/hw/rtl/cache/VX_cache_miss_resrv.v index dbe3665f..288be4fc 100644 --- a/hw/rtl/cache/VX_cache_miss_resrv.v +++ b/hw/rtl/cache/VX_cache_miss_resrv.v @@ -66,7 +66,14 @@ module VX_cache_miss_resrv #( wire enqueue_possible = !miss_resrv_full; wire [`LOG2UP(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr; + wire qual_mrvq_init = mrvq_push && mrvq_init_ready_state; + + `IGNORE_WARNINGS_BEGIN + wire [31:0] make_ready_push_full; + `IGNORE_WARNINGS_END + reg [MRVQ_SIZE-1:0] make_ready; + reg [MRVQ_SIZE-1:0] make_ready_push; reg [MRVQ_SIZE-1:0] valid_address_match; genvar i; @@ -89,7 +96,10 @@ module VX_cache_miss_resrv #( wire mrvq_push = miss_add && enqueue_possible && (MRVQ_SIZE != 2); wire mrvq_pop = miss_resrv_pop && dequeue_possible; - wire update_ready = (| make_ready); + wire update_ready = (|make_ready); + + assign make_ready_push_full = ({31'b0, qual_mrvq_init} << enqueue_index); + assign make_ready_push = make_ready_push_full[MRVQ_SIZE-1:0]; always @(posedge clk) begin if (reset) begin @@ -109,7 +119,7 @@ module VX_cache_miss_resrv #( // update entry as 'ready' during DRAM fill response if (update_ready) begin - ready_table <= ready_table | make_ready; + ready_table <= ready_table | make_ready | make_ready_push; end if (mrvq_pop) begin