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Merge branch 'master' of https://github.gatech.edu/casl/Vortex

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This commit is contained in:
Blaise Tine
2021-09-10 06:03:32 -04:00
parent 170c5d0c8a 5192846c72
commit 0dfdf6cd4d
24 changed files with 571 additions and 157 deletions
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88
hw/rtl/libs/VX_axi_adapter.v Normal file
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@@ -0,0 +1,88 @@
`include "VX_define.vh"
module VX_axi_adapter #(
parameter VX_DATA_WIDTH = 512,
parameter VX_ADDR_WIDTH = (32 - $clog2(VX_DATA_WIDTH/8)),
parameter VX_TAG_WIDTH = 8,
parameter AXI_DATA_WIDTH = VX_DATA_WIDTH,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_TID_WIDTH = VX_TAG_WIDTH,
localparam VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8),
localparam AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
) (
// Vortex request
input wire mem_req_valid,
input wire mem_req_rw,
input wire [VX_BYTEEN_WIDTH-1:0] mem_req_byteen,
input wire [VX_ADDR_WIDTH-1:0] mem_req_addr,
input wire [VX_DATA_WIDTH-1:0] mem_req_data,
input wire [VX_TAG_WIDTH-1:0] mem_req_tag,
// Vortex response
input wire mem_rsp_ready,
output wire mem_rsp_valid,
output wire [VX_DATA_WIDTH-1:0] mem_rsp_data,
output wire [VX_TAG_WIDTH-1:0] mem_rsp_tag,
output wire mem_req_ready,
// AXI write request
output wire m_axi_wvalid,
output wire m_axi_awvalid,
output wire [AXI_TID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst,
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb,
input wire m_axi_wready,
input wire m_axi_awready,
// AXI read request
output wire m_axi_arvalid,
output wire [AXI_TID_WIDTH-1:0] m_axi_arid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst,
input wire m_axi_arready,
// AXI read response
input wire m_axi_rvalid,
input wire [AXI_TID_WIDTH-1:0] m_axi_rid,
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
output wire m_axi_rready
);
localparam AXSIZE = $clog2(VX_DATA_WIDTH/8);
`STATIC_ASSERT((AXI_DATA_WIDTH == VX_DATA_WIDTH), ("invalid parameter"))
`STATIC_ASSERT((AXI_TID_WIDTH == VX_TAG_WIDTH), ("invalid parameter"))
// AXI write channel
assign m_axi_wvalid = mem_req_valid & mem_req_rw;
assign m_axi_awvalid = mem_req_valid & mem_req_rw;
assign m_axi_awid = mem_req_tag;
assign m_axi_awaddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE;
assign m_axi_awlen = 8'b00000000;
assign m_axi_awsize = 3'(AXSIZE);
assign m_axi_awburst = 2'b00;
assign m_axi_wdata = mem_req_data;
assign m_axi_wstrb = mem_req_byteen;
// AXI read channel
assign m_axi_arvalid = mem_req_valid & ~mem_req_rw;
assign m_axi_arid = mem_req_tag;
assign m_axi_araddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE;
assign m_axi_arlen = 8'b00000000;
assign m_axi_arsize = 3'(AXSIZE);
assign m_axi_arburst = 2'b00;
assign m_axi_rready = mem_rsp_ready;
// Vortex inputs
assign mem_rsp_valid = m_axi_rvalid;
assign mem_rsp_tag = m_axi_rid;
assign mem_rsp_data = m_axi_rdata;
assign mem_req_ready = mem_req_rw ? (m_axi_awready && m_axi_wready) : m_axi_arready;
endmodule

8
hw/rtl/libs/VX_dp_ram.v
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@@ -5,7 +5,7 @@ module VX_dp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter OUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0,
@@ -35,7 +35,7 @@ module VX_dp_ram #(
`ifdef SYNTHESIS
if (LUTRAM) begin
if (OUTPUT_REG) begin
if (OUT_REG) begin
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];
@@ -90,7 +90,7 @@ module VX_dp_ram #(
end
end
end else begin
if (OUTPUT_REG) begin
if (OUT_REG) begin
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
@@ -173,7 +173,7 @@ module VX_dp_ram #(
end
end
`else
if (OUTPUT_REG) begin
if (OUT_REG) begin
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];

14
hw/rtl/libs/VX_elastic_buffer.v
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@@ -4,7 +4,7 @@
module VX_elastic_buffer #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter OUTPUT_REG = 0,
parameter OUT_REG = 0,
parameter LUTRAM = 0
) (
input wire clk,
@@ -32,8 +32,8 @@ module VX_elastic_buffer #(
end else if (SIZE == 2) begin
VX_skid_buffer #(
.DATAW (DATAW),
.OUTPUT_REG (OUTPUT_REG)
.DATAW (DATAW),
.OUT_REG (OUT_REG)
) queue (
.clk (clk),
.reset (reset),
@@ -53,10 +53,10 @@ module VX_elastic_buffer #(
wire pop = valid_out && ready_out;
VX_fifo_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (OUTPUT_REG),
.LUTRAM (LUTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.OUT_REG (OUT_REG),
.LUTRAM (LUTRAM)
) queue (
.clk (clk),
.reset (reset),

22
hw/rtl/libs/VX_fifo_queue.v
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@@ -8,7 +8,7 @@ module VX_fifo_queue #(
parameter ALM_EMPTY = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter OUTPUT_REG = 0,
parameter OUT_REG = 0,
parameter LUTRAM = 1
) (
input wire clk,
@@ -103,7 +103,7 @@ module VX_fifo_queue #(
if (SIZE == 2) begin
if (0 == OUTPUT_REG) begin
if (0 == OUT_REG) begin
reg [DATAW-1:0] shift_reg [1:0];
@@ -138,7 +138,7 @@ module VX_fifo_queue #(
end else begin
if (0 == OUTPUT_REG) begin
if (0 == OUT_REG) begin
reg [ADDRW-1:0] rd_ptr_r;
reg [ADDRW-1:0] wr_ptr_r;
@@ -154,10 +154,10 @@ module VX_fifo_queue #(
end
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (0),
.LUTRAM (LUTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.OUT_REG (0),
.LUTRAM (LUTRAM)
) dp_ram (
.clk(clk),
.wren (push),
@@ -197,10 +197,10 @@ module VX_fifo_queue #(
end
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (0),
.LUTRAM (LUTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.OUT_REG (0),
.LUTRAM (LUTRAM)
) dp_ram (
.clk (clk),
.wren (push),

4
hw/rtl/libs/VX_skid_buffer.v
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@@ -5,7 +5,7 @@ module VX_skid_buffer #(
parameter DATAW = 1,
parameter PASSTHRU = 0,
parameter NOBACKPRESSURE = 0,
parameter OUTPUT_REG = 0
parameter OUT_REG = 0
) (
input wire clk,
input wire reset,
@@ -51,7 +51,7 @@ module VX_skid_buffer #(
end else begin
if (OUTPUT_REG) begin
if (OUT_REG) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;

8
hw/rtl/libs/VX_sp_ram.v
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@@ -5,7 +5,7 @@ module VX_sp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter OUT_REG = 0,
parameter NO_RWCHECK = 0,
parameter ADDRW = $clog2(SIZE),
parameter LUTRAM = 0,
@@ -34,7 +34,7 @@ module VX_sp_ram #(
`ifdef SYNTHESIS
if (LUTRAM) begin
if (OUTPUT_REG) begin
if (OUT_REG) begin
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
@@ -90,7 +90,7 @@ module VX_sp_ram #(
end
end
end else begin
if (OUTPUT_REG) begin
if (OUT_REG) begin
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
@@ -173,7 +173,7 @@ module VX_sp_ram #(
end
end
`else
if (OUTPUT_REG) begin
if (OUT_REG) begin
reg [DATAW-1:0] rdata_r;
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] ram [SIZE-1:0];

28
hw/rtl/libs/VX_stream_arbiter.v
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@@ -98,31 +98,13 @@ module VX_stream_arbiter #(
if (LANES > 1) begin
wire [NUM_REQS-1:0][(LANES * (1 + DATAW))-1:0] valid_data_in;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign valid_data_in[i] = {valid_in[i], data_in[i]};
end
VX_mux #(
.DATAW (LANES * (1 + DATAW)),
.N (NUM_REQS)
) data_in_mux (
.data_in (valid_data_in),
.sel_in (sel_index),
.data_out ({valid_in_sel, data_in_sel})
);
assign {valid_in_sel, data_in_sel} = valid_data_in[sel_index];
`UNUSED_VAR (sel_valid)
end else begin
VX_mux #(
.DATAW (DATAW),
.N (NUM_REQS)
) data_in_mux (
.data_in (data_in),
.sel_in (sel_index),
.data_out (data_in_sel)
);
assign data_in_sel = data_in[sel_index];
assign valid_in_sel = sel_valid;
end
@@ -132,9 +114,9 @@ module VX_stream_arbiter #(
for (genvar i = 0; i < LANES; ++i) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (0 == BUFFERED),
.OUTPUT_REG (2 == BUFFERED)
.DATAW (DATAW),
.PASSTHRU (0 == BUFFERED),
.OUT_REG (2 == BUFFERED)
) out_buffer (
.clk (clk),
.reset (reset),

6
hw/rtl/libs/VX_stream_demux.v
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@@ -37,9 +37,9 @@ module VX_stream_demux #(
for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (0 == BUFFERED),
.OUTPUT_REG (2 == BUFFERED)
.DATAW (DATAW),
.PASSTHRU (0 == BUFFERED),
.OUT_REG (2 == BUFFERED)
) out_buffer (
.clk (clk),
.reset (reset),