88 lines
3.6 KiB
Verilog
88 lines
3.6 KiB
Verilog
`include "VX_define.vh"
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module VX_axi_adapter #(
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parameter VX_DATA_WIDTH = 512,
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parameter VX_ADDR_WIDTH = (32 - $clog2(VX_DATA_WIDTH/8)),
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parameter VX_TAG_WIDTH = 8,
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parameter AXI_DATA_WIDTH = VX_DATA_WIDTH,
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parameter AXI_ADDR_WIDTH = 32,
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parameter AXI_TID_WIDTH = VX_TAG_WIDTH,
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localparam VX_BYTEEN_WIDTH = (VX_DATA_WIDTH / 8),
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localparam AXI_STROBE_WIDTH = (AXI_DATA_WIDTH / 8)
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) (
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// Vortex request
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input wire mem_req_valid,
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input wire mem_req_rw,
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input wire [VX_BYTEEN_WIDTH-1:0] mem_req_byteen,
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input wire [VX_ADDR_WIDTH-1:0] mem_req_addr,
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input wire [VX_DATA_WIDTH-1:0] mem_req_data,
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input wire [VX_TAG_WIDTH-1:0] mem_req_tag,
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// Vortex response
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input wire mem_rsp_ready,
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output wire mem_rsp_valid,
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output wire [VX_DATA_WIDTH-1:0] mem_rsp_data,
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output wire [VX_TAG_WIDTH-1:0] mem_rsp_tag,
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output wire mem_req_ready,
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// AXI write request
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output wire m_axi_wvalid,
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output wire m_axi_awvalid,
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output wire [AXI_TID_WIDTH-1:0] m_axi_awid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
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output wire [7:0] m_axi_awlen,
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output wire [2:0] m_axi_awsize,
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output wire [1:0] m_axi_awburst,
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output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
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output wire [AXI_STROBE_WIDTH-1:0] m_axi_wstrb,
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input wire m_axi_wready,
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input wire m_axi_awready,
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// AXI read request
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output wire m_axi_arvalid,
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output wire [AXI_TID_WIDTH-1:0] m_axi_arid,
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output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [7:0] m_axi_arlen,
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output wire [2:0] m_axi_arsize,
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output wire [1:0] m_axi_arburst,
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input wire m_axi_arready,
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// AXI read response
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input wire m_axi_rvalid,
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input wire [AXI_TID_WIDTH-1:0] m_axi_rid,
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input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
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output wire m_axi_rready
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);
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localparam AXSIZE = $clog2(VX_DATA_WIDTH/8);
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`STATIC_ASSERT((AXI_DATA_WIDTH == VX_DATA_WIDTH), ("invalid parameter"))
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`STATIC_ASSERT((AXI_TID_WIDTH == VX_TAG_WIDTH), ("invalid parameter"))
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// AXI write channel
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assign m_axi_wvalid = mem_req_valid & mem_req_rw;
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assign m_axi_awvalid = mem_req_valid & mem_req_rw;
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assign m_axi_awid = mem_req_tag;
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assign m_axi_awaddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE;
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assign m_axi_awlen = 8'b00000000;
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assign m_axi_awsize = 3'(AXSIZE);
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assign m_axi_awburst = 2'b00;
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assign m_axi_wdata = mem_req_data;
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assign m_axi_wstrb = mem_req_byteen;
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// AXI read channel
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assign m_axi_arvalid = mem_req_valid & ~mem_req_rw;
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assign m_axi_arid = mem_req_tag;
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assign m_axi_araddr = AXI_ADDR_WIDTH'(mem_req_addr) << AXSIZE;
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assign m_axi_arlen = 8'b00000000;
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assign m_axi_arsize = 3'(AXSIZE);
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assign m_axi_arburst = 2'b00;
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assign m_axi_rready = mem_rsp_ready;
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// Vortex inputs
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assign mem_rsp_valid = m_axi_rvalid;
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assign mem_rsp_tag = m_axi_rid;
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assign mem_rsp_data = m_axi_rdata;
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assign mem_req_ready = mem_req_rw ? (m_axi_awready && m_axi_wready) : m_axi_arready;
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endmodule |