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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 08:01:46 -04:00
parent 62c1c3fdbb
commit 0c81a3ae19
10 changed files with 94 additions and 94 deletions
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28
hw/rtl/generic_cache/VX_cache.v
View File

@@ -54,10 +54,10 @@ module VX_cache #(
// Core request
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0][2:0] core_req_mem_read,
input wire [NUM_REQUESTS-1:0][2:0] core_req_mem_write,
input wire [NUM_REQUESTS-1:0][2:0] core_req_read,
input wire [NUM_REQUESTS-1:0][2:0] core_req_write,
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_writedata,
input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_data,
output wire core_req_ready,
// Core request meta data
@@ -69,10 +69,10 @@ module VX_cache #(
// Core response
output wire [NUM_REQUESTS-1:0] core_rsp_valid,
output wire [4:0] core_rsp_req_rd,
output wire [1:0] core_rsp_req_wb,
output wire [NUM_REQUESTS-1:0][31:0] core_rsp_address,
output wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_readdata,
output wire [4:0] core_rsp_read,
output wire [1:0] core_rsp_write,
output wire [NUM_REQUESTS-1:0][31:0] core_rsp_addr,
output wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_data,
input wire core_rsp_ready,
// Core response meta data
@@ -230,11 +230,11 @@ module VX_cache #(
.core_rsp_ready (core_rsp_ready),
.core_rsp_valid (core_rsp_valid),
.core_rsp_req_rd (core_rsp_req_rd),
.core_rsp_req_wb (core_rsp_req_wb),
.core_rsp_read (core_rsp_read),
.core_rsp_write (core_rsp_write),
.core_rsp_warp_num (core_rsp_warp_num),
.core_rsp_readdata (core_rsp_readdata),
.core_rsp_address (core_rsp_address),
.core_rsp_data (core_rsp_data),
.core_rsp_addr (core_rsp_addr),
.core_rsp_pc (core_rsp_pc)
);
@@ -303,13 +303,13 @@ module VX_cache #(
// Core Req
assign curr_bank_valids = per_bank_valids[curr_bank];
assign curr_bank_addr = core_req_addr;
assign curr_bank_writedata = core_req_writedata;
assign curr_bank_writedata = core_req_data;
assign curr_bank_rd = core_req_rd;
assign curr_bank_wb = core_req_wb;
assign curr_bank_pc = core_req_pc;
assign curr_bank_warp_num = core_req_warp_num;
assign curr_bank_mem_read = core_req_mem_read;
assign curr_bank_mem_write = core_req_mem_write;
assign curr_bank_mem_read = core_req_read;
assign curr_bank_mem_write = core_req_write;
assign per_bank_reqq_full[curr_bank] = curr_bank_reqq_full;
// Core WB

24
hw/rtl/generic_cache/VX_cache_wb_sel_merge.v
View File

@@ -56,12 +56,12 @@ module VX_cache_wb_sel_merge #(
// Core Writeback
input wire core_rsp_ready,
output reg [NUM_REQUESTS-1:0] core_rsp_valid,
output reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_readdata,
output reg [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_rsp_data,
output reg [NUM_REQUESTS-1:0][31:0] core_rsp_pc,
output wire [4:0] core_rsp_req_rd,
output wire [1:0] core_rsp_req_wb,
output wire [4:0] core_rsp_read,
output wire [1:0] core_rsp_write,
output wire [`NW_BITS-1:0] core_rsp_warp_num,
output reg [NUM_REQUESTS-1:0][31:0] core_rsp_address
output reg [NUM_REQUESTS-1:0][31:0] core_rsp_addr
);
reg [NUM_BANKS-1:0] per_bank_wb_pop_unqual;
@@ -86,17 +86,17 @@ module VX_cache_wb_sel_merge #(
.found (found_bank)
);
assign core_rsp_req_rd = per_bank_wb_rd[main_bank_index];
assign core_rsp_req_wb = per_bank_wb_wb[main_bank_index];
assign core_rsp_read = per_bank_wb_rd[main_bank_index];
assign core_rsp_write = per_bank_wb_wb[main_bank_index];
assign core_rsp_warp_num = per_bank_wb_warp_num[main_bank_index];
integer this_bank;
generate
always @(*) begin
core_rsp_valid = 0;
core_rsp_readdata = 0;
core_rsp_data = 0;
core_rsp_pc = 0;
core_rsp_address = 0;
core_rsp_addr = 0;
for (this_bank = 0; this_bank < NUM_BANKS; this_bank = this_bank + 1) begin
if ((FUNC_ID == `L2FUNC_ID) || (FUNC_ID == `L3FUNC_ID)) begin
if (found_bank
@@ -105,9 +105,9 @@ module VX_cache_wb_sel_merge #(
&& ((main_bank_index == `LOG2UP(NUM_BANKS)'(this_bank))
|| (per_bank_wb_tid[this_bank] != per_bank_wb_tid[main_bank_index]))) begin
core_rsp_valid[per_bank_wb_tid[this_bank]] = 1;
core_rsp_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_rsp_data[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_rsp_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank];
core_rsp_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank];
core_rsp_addr[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank];
per_bank_wb_pop_unqual[this_bank] = 1;
end else begin
per_bank_wb_pop_unqual[this_bank] = 0;
@@ -121,9 +121,9 @@ module VX_cache_wb_sel_merge #(
&& (per_bank_wb_rd[this_bank] == per_bank_wb_rd[main_bank_index])
&& (per_bank_wb_warp_num[this_bank] == per_bank_wb_warp_num[main_bank_index])) begin
core_rsp_valid[per_bank_wb_tid[this_bank]] = 1;
core_rsp_readdata[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_rsp_data[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_rsp_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank];
core_rsp_address[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank];
core_rsp_addr[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank];
per_bank_wb_pop_unqual[this_bank] = 1;
end else begin
per_bank_wb_pop_unqual[this_bank] = 0;