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few updates

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This commit is contained in:
Blaise Tine
2020-06-23 09:28:24 -07:00
parent f80e7c31de
commit 0a01385a2c
24 changed files with 228 additions and 226 deletions
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17
hw/rtl/VX_gpr_ram.v
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@@ -3,27 +3,24 @@
module VX_gpr_ram (
input wire clk,
input wire reset,
input wire we,
input wire [4:0] waddr,
input wire [4:0] raddr1,
input wire [4:0] raddr2,
input wire [`NUM_THREADS-1:0] be,
input wire [`NUM_THREADS-1:0] we,
input wire [`NUM_THREADS-1:0][31:0] wdata,
output reg [`NUM_THREADS-1:0][31:0] q1,
output reg [`NUM_THREADS-1:0][31:0] q2
);
reg [`NUM_THREADS-1:0][31:0] ram[31:0];
integer i;
`UNUSED_VAR(reset)
always @(posedge clk) begin
if (we) begin
for (i = 0; i < `NUM_THREADS; i++) begin
if (be[i]) begin
ram[waddr][i] <= wdata[i];
end
genvar i;
for (i = 0; i < `NUM_THREADS; i++) begin
always @(posedge clk) begin
if (we[i]) begin
ram[waddr][i] <= wdata[i];
end
end
end