32 lines
799 B
Verilog
32 lines
799 B
Verilog
`include "VX_define.vh"
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module VX_gpr_ram (
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input wire clk,
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input wire reset,
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input wire [4:0] waddr,
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input wire [4:0] raddr1,
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input wire [4:0] raddr2,
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input wire [`NUM_THREADS-1:0] we,
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input wire [`NUM_THREADS-1:0][31:0] wdata,
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output reg [`NUM_THREADS-1:0][31:0] q1,
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output reg [`NUM_THREADS-1:0][31:0] q2
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);
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reg [`NUM_THREADS-1:0][31:0] ram[31:0];
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`UNUSED_VAR(reset)
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genvar i;
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for (i = 0; i < `NUM_THREADS; i++) begin
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always @(posedge clk) begin
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if (we[i]) begin
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ram[waddr][i] <= wdata[i];
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end
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end
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end
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assign q1 = ram[raddr1];
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assign q2 = ram[raddr2];
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endmodule
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