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Fixed incorrect valid and'ing in execute

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This commit is contained in:
felsabbagh3
2020-03-03 20:57:20 -08:00
parent a47f7c11ec
commit 08986bf1dc
2 changed files with 4 additions and 4 deletions
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2
rtl/VX_execute_unit.v
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@@ -115,7 +115,7 @@ module VX_execute_unit (
// Actual Writeback // Actual Writeback
assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd; assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd;
assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb; assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb;
assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid && !internal_stall; assign VX_inst_exec_wb.wb_valid = VX_exec_unit_req.valid & {`NT{!internal_stall}};
assign VX_inst_exec_wb.wb_warp_num = VX_exec_unit_req.warp_num; assign VX_inst_exec_wb.wb_warp_num = VX_exec_unit_req.warp_num;
assign VX_inst_exec_wb.alu_result = VX_exec_unit_req.jal ? duplicate_PC_data : alu_result; assign VX_inst_exec_wb.alu_result = VX_exec_unit_req.jal ? duplicate_PC_data : alu_result;

6
rtl/VX_scheduler.v
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@@ -50,9 +50,9 @@ module VX_scheduler (
wire rename_valid = rs1_rename_qual || rs2_rename_qual || rd_rename_qual; wire rename_valid = rs1_rename_qual || rs2_rename_qual || rd_rename_qual;
assign schedule_delay = ((rename_valid) && (|VX_bckE_req.valid)) assign schedule_delay = ((rename_valid) && (|VX_bckE_req.valid))
|| (memory_delay && is_mem) || (memory_delay && is_mem)
|| (gpr_stage_delay && (is_mem || is_exec)) || (gpr_stage_delay && (is_mem || is_exec))
|| (exec_delay && is_exec); || (exec_delay && is_exec);
integer i; integer i;
integer w; integer w;