45 lines
1.4 KiB
Scala
45 lines
1.4 KiB
Scala
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package freechips.rocketchip.tilelink
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
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import org.chipsalliance.cde.config.{Parameters, Field, Config}
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// class class, consumed by WithGPUTacer config and GPUTracerKey
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case class GPUTracerConfig(numLanes: Int, traceFile : String) // FIXME, add lane number and file name
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case object GPUTracerKey extends Field[Option[GPUTracerConfig]](None)
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// Both LazyModule of Tracer and Impl are both in Coalescing.scala
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//The trait is attached to DigitalTop of Chipyard system, informing it indeed has the ability
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//to attach GPU tracer node onto the system bus
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trait CanHaveGPUTracer { this: BaseSubsystem =>
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implicit val p: Parameters
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//p(GPUTracerKey) is the mechnimism to pass Config's parameter down to lazymodule
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p(GPUTracerKey) .map { k =>
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val config = p(GPUTracerKey).get
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val tracer = LazyModule(new MemTraceDriver(defaultConfig, config.traceFile)(p))
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// Must use :=* to ensure the N edges from Tracer doesn't get merged into 1 when connecting to SBus
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sbus.fromPort(Some("gpu-tracer"))() :=* tracer.node
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}
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}
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//This is used by Chip Level Config, the config which creates the SoC
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class WithGPUTracer(numLanes: Int, traceFile : String) extends Config((site, here, up) => {
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case GPUTracerKey => Some( GPUTracerConfig(numLanes, traceFile) )
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}
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)
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