106 lines
3.5 KiB
Verilog
106 lines
3.5 KiB
Verilog
// FIXME hardcoded
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`define MEMTRACE_DATA_WIDTH 64
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`define MAX_NUM_LANES 32
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`define MEMTRACE_LOGSIZE_WIDTH 8
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import "DPI-C" function void memtrace_init(
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input string filename,
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input bit has_source
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);
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// Make sure to sync the parameters for:
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// (1) import "DPI-C" declaration
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// (2) C function declaration
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// (3) DPI function calls inside initial/always blocks
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import "DPI-C" function void memtrace_query
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(
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input bit trace_read_ready,
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input longint trace_read_cycle,
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input int trace_read_lane_id,
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output bit trace_read_valid,
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output longint trace_read_address,
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output bit trace_read_is_store,
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output byte trace_read_size,
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output longint trace_read_data,
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output bit trace_read_finished
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);
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module SimMemTrace #(parameter FILENAME = "undefined",
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NUM_LANES = 4,
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HAS_SOURCE = 0) (
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input clock,
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input reset,
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// Chisel module needs to tell Verilog blackbox which cycle to read
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input [64-1:0] trace_read_cycle,
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// These have to match the IO port name of the Chisel wrapper module.
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input trace_read_ready,
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output [NUM_LANES-1:0] trace_read_valid,
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output [`MEMTRACE_DATA_WIDTH*NUM_LANES-1:0] trace_read_address,
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output [NUM_LANES-1:0] trace_read_is_store,
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output [`MEMTRACE_LOGSIZE_WIDTH*NUM_LANES-1:0] trace_read_size,
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output [`MEMTRACE_DATA_WIDTH*NUM_LANES-1:0] trace_read_data,
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output trace_read_finished
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);
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bit __in_valid [NUM_LANES-1:0];
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longint __in_address [NUM_LANES-1:0];
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bit __in_is_store [NUM_LANES-1:0];
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reg [`MEMTRACE_LOGSIZE_WIDTH-1:0] __in_size [NUM_LANES-1:0];
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longint __in_data [NUM_LANES-1:0];
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bit __in_finished;
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genvar g;
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generate
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for (g = 0; g < NUM_LANES; g = g + 1) begin
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assign trace_read_valid[g] = __in_valid[g];
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assign trace_read_address[`MEMTRACE_DATA_WIDTH*(g+1)-1:`MEMTRACE_DATA_WIDTH*g] = __in_address[g];
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assign trace_read_is_store[g] = __in_is_store[g];
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assign trace_read_size[`MEMTRACE_LOGSIZE_WIDTH*(g+1)-1:`MEMTRACE_LOGSIZE_WIDTH*g] = __in_size[g];
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assign trace_read_data[`MEMTRACE_DATA_WIDTH*(g+1)-1:`MEMTRACE_DATA_WIDTH*g] = __in_data[g];
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end
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endgenerate
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assign trace_read_finished = __in_finished;
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initial begin
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/* $value$plusargs("uartlog=%s", __uartlog); */
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memtrace_init(FILENAME, HAS_SOURCE);
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end
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always @(posedge clock) begin
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if (reset) begin
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for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
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__in_valid[tid] = 1'b0;
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__in_address[tid] = `MEMTRACE_DATA_WIDTH'b0;
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__in_is_store[tid] = 1'b0;
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__in_size[tid] = `MEMTRACE_LOGSIZE_WIDTH'b0;
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__in_data[tid] = `MEMTRACE_DATA_WIDTH'b0;
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end
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__in_finished = 1'b0;
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end else begin
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// We have to write to __in_ regs only when trace_read_ready, or
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// otherwise we might overwrite lines that were previously valid
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// but the downstream missed by being not ready.
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if (trace_read_ready) begin
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for (integer tid = 0; tid < NUM_LANES; tid = tid + 1) begin
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memtrace_query(
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trace_read_ready,
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trace_read_cycle,
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tid,
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__in_valid[tid],
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__in_address[tid],
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__in_is_store[tid],
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__in_size[tid],
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__in_data[tid],
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__in_finished
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);
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end
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end
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end
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end
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endmodule
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