Hansung Kim
e7a008ec74
Rename #define constants in SimMemTrace
...
... to prevent collision with constants of the same name in other
verilog sources.
2023-10-01 20:58:49 -07:00
Hansung Kim
5ee4154f26
Fix C/verilog argument size mismatch on Verilator
2023-10-01 12:12:11 -07:00
Hansung Kim
1886aefcc1
Parameterize tracefile has_source from Config
2023-05-09 22:22:27 -07:00
Hansung Kim
54a3e3cf72
Initiate memtrace DPI only when trace_read_ready
...
This is required because otherwise we might overwrite into
the Verilog registers that contain a valid trace line that
was missed by downstream when it was not ready. Basically
whenever trace_read_cycle stalls, we also want to stall
__in_* registers.
2023-05-08 14:34:52 -07:00
Hansung Kim
6b97b77572
Revert SimMemTrace.v to use posedge clock
...
Doing function calls inside @(*) causes lint errors. Instead, remove
staging registers to eliminate 1 cycle latency between DPI call and
when output is visible to Chisel.
2023-05-08 00:14:48 -07:00
Vamber Yang
8ccaf3864d
Support for more realistic MemTracer step2 (DONE), make Verilog Blackbox DPI output data immediately and make .cc file maintain pointer when downstream is not ready
2023-05-02 22:06:16 -07:00
Vamber Yang
be0fcbd23b
Support for more realistic MemTracer step 1, allow Chisel MemTracer to input read_cycle to Verilog blackbox
2023-05-02 14:01:19 -07:00
Hansung Kim
8a7e6f1391
Replace hardcoded trace widths with proper params
2023-04-21 18:20:16 -07:00
Hansung Kim
d4a51cfee5
Log source ID in the trace
2023-04-17 18:43:17 -07:00
Hansung Kim
8e763b512a
Relay full trace line info to DPI
2023-04-12 13:54:59 -07:00
Hansung Kim
1057ed59d3
Parse log2(size) from trace; set is_store from TL opcode
2023-04-11 18:23:50 -07:00
Hansung Kim
71f334bb22
Fix size parsing from memtrace
2023-04-11 17:36:45 -07:00
Hansung Kim
dca52ace0b
Fix verilog lint error
2023-04-10 20:37:26 -07:00
Hansung Kim
9bfb813e1b
Thread -> Lane
...
"thread" is confusing, unify to lane when denoting a hardware SIMD lane
inside a single warp.
2023-03-09 22:09:21 -08:00
Vamber Yang
0de09daa05
MemTracer able to read and write according to trace file, also support thread_id skipping in trace file
2023-03-08 17:34:10 -08:00
Hansung Kim
db9be56191
Properly connect each lane to TL node
2023-03-05 00:18:29 -08:00
Hansung Kim
5f55a7578f
Recover lost changes
2023-03-03 22:36:54 -08:00
Hansung Kim
9025729c0e
Emit address in addition to cycle
2023-02-27 17:36:54 -08:00
Hansung Kim
0ebaed5f1b
Communicate trace cycle data from C++ to Chisel
2023-02-27 14:40:49 -08:00
Hansung Kim
72de4bca66
Initial parsing of memory trace file in C++
2023-02-27 13:47:30 -08:00
Hansung Kim
80e4b5c734
Set up simple DPI for trace-driven testing
2023-02-26 20:39:19 -08:00
